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quad channel, 16-bit, serial input, 4 ma to 20 ma and voltage output dac, dynamic power control ad5755 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features 16-bit resolution and monotonicity dynamic power control for thermal management current and voltage output pins connectable to a single terminal current output ranges: 0 ma to 20 ma, 4 ma to 20 ma, or 0 ma to 24 ma 0.05% total unadjusted error (tue) maximum voltage output ranges (with 20% overrange): 0 v to 5 v, 0 v to 10 v, 5 v, and 10 v 0.04% total unadjusted error (tue) maximum user programmable offset and gain on-chip diagnostics on-chip reference (10 ppm/c maximum) ?40c to +105c temperature range applications process control actuator control plcs general description the ad5755 is a quad, voltage and current output dac that operates with a power supply range from ?26.4 v to +33 v. on-chip dynamic power control minimizes package power dissipation in current mode. this is achieved by regulating the voltage on the output driver from 7.4 v to 29.5 v using a dc-to- dc boost converter optimized for minimum on chip power dissipation. the part uses a versatile 3-wire serial interface that operates at clock rates of up to 30 mhz and is compatible with standard spi, qspi?, microwire?, dsp, and microcontroller inter- face standards. the interface also features optional crc-8 packet error checking, as well as a watchdog timer that monitors activity on the interface. product highlights 1. dynamic power control for thermal management. 2. 16-bit performance. 3. multichannel. companion products product family: ad5755-1 , ad5757 external references: adr445 , adr02 digital isolators: adum1410 , adum1411 power: adp2302 , adp2303 additional companion products on the ad5755 product page functional block diagram 07304-100 ad5755 av ss ?15v agnd av dd +15v a v cc 5.0v dv dd dgnd ldac clear sclk sdin sync sdo fault dc-to-dc converter digital interface reference current and voltage output range scaling alert refout refin ad1 ad0 dac a sw x v boost_x gain reg a offset reg a r set_x +v sense_x ?v sense_x v out_x i out_x dac channel b dac channel a dac channel c dac channel d 7.4v to 29.5v + notes 1. x = a, b, c, and d. figure 1.
ad5755 rev. 0 | page 2 of 48 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? companion products ....................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? detailed functional block diagram .............................................. 3 ? specifications..................................................................................... 4 ? ac performance characteristics ................................................ 7 ? timing characteristics ................................................................ 8 ? absolute maximum ratings.......................................................... 11 ? esd caution................................................................................ 11 ? pin configuration and function descriptions........................... 12 ? typical performance characteristics ........................................... 15 ? voltage outputs .......................................................................... 15 ? current outputs ......................................................................... 19 ? dc-to-dc block......................................................................... 23 ? reference ..................................................................................... 24 ? general......................................................................................... 25 ? terminology .................................................................................... 26 ? theory of operation ...................................................................... 28 ? dac architecture....................................................................... 28 ? power-on state of ad5755....................................................... 28 ? serial interface ............................................................................ 29 ? transfer function ....................................................................... 29 ? registers ........................................................................................... 30 ? programming sequence to write/enable the output correctly ...................................................................................... 31 ? changing and reprogramming the range ............................. 31 ? data registers ............................................................................. 32 ? control registers........................................................................ 34 ? readback operation .................................................................. 37 ? device features............................................................................... 39 ? output fault................................................................................ 39 ? voltage output short-circuit protection................................ 39 ? digital offset and gain control............................................... 39 ? status readback during a write .............................................. 39 ? asynchronous clear................................................................... 40 ? packet error checking............................................................... 40 ? watchdog timer......................................................................... 40 ? output alert................................................................................ 40 ? internal reference ...................................................................... 40 ? external current setting resistor ............................................ 40 ? digital slew rate control.......................................................... 41 ? power dissipation control......................................................... 41 ? dc-to-dc converters............................................................... 41 ? ai cc supply requirementsstatic............................................ 43 ? ai cc supply requirementsslewing ...................................... 43 ? applications information .............................................................. 45 ? voltage and current output ranges on the same terminal 45 ? current output mode with internal r set ................................ 45 ? precision voltage reference selection..................................... 45 ? driving inductive loads............................................................ 46 ? transient voltage protection .................................................... 46 ? microprocessor interfacing....................................................... 46 ? layout guidelines....................................................................... 46 ? galvanically isolated interface ................................................. 47 ? outline dimensions ....................................................................... 48 ? ordering guide .......................................................................... 48 ? revision history 5/11revision 0: initial version
ad5755 rev. 0 | page 3 of 48 detailed functional block diagram ad5755 av ss ?15v agnd av dd +15v av cc 5.0v dv dd dgnd ldac clear sclk sdin sync sdo fault dc-to-dc converter power control input shift register and control status register power-on reset reference buffers dac reg a input reg a vref watchdog timer (spi activity) vout range scaling alert refout refin ad1 ad0 dac a 16 16 sw a v boost_a gain reg a offset reg a r1 r2 r3 r set_a v out_a i out_b , i out_c , i out_d r set_b , r set_c , r set_d +v sense_b , +v sense_ c , +v sense_ d v out_b , v out_c , v out_d i out_a +v sense_a ?v sense_a dac channel b dac channel a dac channel c dac channel d sw b , sw c , sw d v boost_b ,v boost_c ,v boost_d 7.4v to 29.5v reg v sen1 v sen2 + 07304-001 figure 2.
ad5755 rev. 0 | page 4 of 48 specifications av dd = v boost_x = 15 v; av ss = ?15 v; dv dd = 2.7 v to 5.5 v; av cc = 4.5 v to 5.5 v; dc-to-dc converter disabled; agnd = dgnd = gndsw x = 0 v; refin = 5 v; voltage outputs: r l = 1 k, c l = 220 pf; current outputs: r l = 300 ; all specifications t min to t max , unless otherwise noted. table 1. parameter 1 min typ max unit test conditions/comments voltage output output voltage ranges 0 5 v 0 10 v av dd must have minimum 2.2 v headroom on output ?5 +5 v ?10 +10 v av dd /av ss must have minimum 2.2 v headroom on output 0 6 v 0 12 v av dd must have minimum 2.2 v headroom on output ?6 +6 v ?12 +12 v av dd /av ss must have minimum 2.2 v headroom on output resolution 16 bits accuracy av ss = ?15 v, loaded and unloaded total unadjusted error (tue) b version ?0.04 +0.04 % fsr ?0.03 0.0032 +0.03 % fsr t a = 25c a version ?0.25 +0.25 % fsr ?0.075 0.02 +0.075 % fsr t a = 25c tue long-term stability 35 ppm fsr drift after 1000 hours, t j = 150c relative accuracy (inl) ?0.006 0.0012 +0.006 % fsr 0 v to 5 v, 0 v to 10 v, 5 v, 10 v ranges ?0.008 0.0012 +0.008 % fsr on overranges differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic zero-scale error ?0.03 0.002 +0.03 % fsr zero-scale tc 2 2 ppm fsr/c bipolar zero error ?0.03 0.002 +0.03 % fsr bipolar zero tc 2 1 ppm fsr/c offset error ?0.03 0.002 +0.03 % fsr offset tc 2 2 ppm fsr/c gain error ?0.03 0.004 +0.03 % fsr gain tc 2 3 ppm fsr/c full-scale error ?0.03 0.002 +0.03 % fsr full-scale tc 2 2 ppm fsr/c output characteristics 2 headroom 1 2.2 v footroom 1 1.4 v output voltage drift vs. time 20 ppm fsr drift after 1000 hours, ? scale output, t j = 150c, av ss = ?15 v short-circuit current 12/6 16/8 ma programmable by user, defaults to 16 ma typical level load 1 k for specified performance
ad5755 rev. 0 | page 5 of 48 parameter 1 min typ max unit test conditions/comments capacitive load stability 10 nf 2 f external compensation capacitor of 220 pf connected dc output impedance 0.06 dc psrr 50 v/v dc crosstalk 24 v current output output current ranges 0 24 ma 0 20 ma 4 20 ma resolution 16 bits accuracy (external r set ) assumes ideal resistor total unadjusted error (tue) b version ?0.05 0.009 +0.05 % fsr a version ?0.2 0.04 +0.2 % fsr tue long-term stability 100 ppm fsr drift after 1000 hours, t j = 150c relative accuracy (inl) ?0.006 +0.006 % fsr differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic offset error ?0.05 0.005 +0.05 % fsr offset error drift 2 4 ppm fsr/c gain error ?0.05 0.004 +0.05 % fsr gain tc 2 3 ppm fsr/c full-scale error ?0.05 0.008 +0.05 % fsr full-scale tc 2 5 ppm fsr/c dc crosstalk 0.0005 % fsr external r set accuracy (internal r set ) total unadjusted error (tue) 3 , 4 b version ?0.14 +0.14 % fsr ?0.11 0.009 +0.11 % fsr t a = 25c a version ?0.35 +0.35 % fsr ?0.2 +0.04 +0.2 % fsr t a = 25c tue long-term stability 180 ppm fsr drift after 1000 hours, t j = 150c relative accuracy (inl) ?0.006 +0.006 % fsr relative accuracy (inl) ?0.004 +0.004 % fsr t a = 25c differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic offset error 3 , 4 ?0.05 +0.05 % fsr ?0.04 0.007 +0.04 % fsr t a = 25c offset error drift 2 6 ppm fsr/c gain error ?0.12 +0.12 % fsr ?0.06 0.002 +0.06 % fsr t a = 25c gain tc 2 9 ppm fsr/c full-scale error 3 , 4 ?0.14 +0.14 % fsr ?0.1 0.007 +0.1 % fsr t a = 25c full-scale tc 2 14 ppm fsr/c dc crosstalk 4 ?0.011 % fsr internal r set
ad5755 rev. 0 | page 6 of 48 parameter 1 min typ max unit test conditions/comments output characteristics 2 current loop compliance voltage v boost_x ? 2.4 v boost_x ? 2.7 v output current drift vs. time drift after 1000 hours, ? scale output, t j = 150c 90 ppm fsr external r set 140 ppm fsr internal r set resistive load 1000 the dc-to-dc converter has been characterized with a maximum load of 1 k, chosen such that compliance is not exceeded; see figure 52 and dc-dc maxv bits in table 25 output impedance 100 m dc psrr 0.02 1 a/v reference input/output reference input 2 reference input voltage 4.95 5 5.05 v for specified performance dc input impedance 45 150 m reference output output voltage 4.995 5 5.005 v t a = 25c reference tc 2 ?10 5 +10 ppm/c output noise (0.1 hz to 10 hz) 2 7 v p-p noise spectral density 2 100 nv/hz at 10 khz output voltage drift vs. time 2 180 ppm drift after 1000 hours, t j = 150c capacitive load 2 1000 nf load current 9 ma see figure 63 short-circuit current 10 ma line regulation 2 3 ppm/v see figure 64 load regulation 2 95 ppm/ma see figure 63 thermal hysteresis 2 160 ppm first temperature cycle 5 ppm second temperature cycle dc-to-dc switch switch on resistance 0.425 switch leakage current 10 na peak current limit 0.8 a oscillator oscillator frequency 11.5 13 14.5 mhz this oscillator is divided down to give the dc-to-dc converter switching frequency maximum duty cycle 89.6 % at 410 khz dc-to-dc switching frequency digital inputs 2 jedec compliant v ih , input high voltage 2 v v il , input low voltage 0.8 v input current ?1 +1 a per pin pin capacitance 2.6 pf per pin digital outputs 2 sdo, alert v ol , output low voltage 0.4 v sinking 200 a v oh , output high voltage dvdd ? 0.5 v sourcing 200 a high impedance leakage current ?1 +1 a high impedance output capacitance 2.5 pf
ad5755 rev. 0 | page 7 of 48 parameter 1 min typ max unit test conditions/comments fault v ol , output low voltage 0.4 v 10 k pull-up resistor to dv dd v ol , output low voltage 0.6 v at 2.5 ma v oh , output high voltage 3.6 v 10 k pull-up resistor to dv dd power requirements av dd 9 33 v av ss ?26.4 ?10.8 v dv dd 2.7 5.5 v av cc 4.5 5.5 v ai dd 8.6 10.5 ma voltage output mode on all channels, output unloaded, over supplies 7 7.5 ma current output mode on all channels, ai ss ?11 ?8.8 ma voltage output mode on all channels, output unloaded, over supplies ?1.7 ma current output mode on all channels di cc 9.2 11 ma v ih = dv dd , v il = dgnd, internal oscillator running, over supplies ai cc 1 ma output unloaded, over supplies i boost 5 2.7 ma per channel, voltage output mode, output unloaded, over supplies 1 ma per channel, current output mode power dissipation 173 mw av dd = 15 v, av ss = ?15 v, dc-to-dc converter enable, current output mo de, outputs disabled 1 temperature range: ?40c to +105c; typical at +25c. 2 guaranteed by design and characterization; not production tested. 3 for current outputs with internal r set , the offset, full-scale, and tue measurements exclude dc crosstalk. the measurements are made with all four channels enabled loaded with the same code. 4 see the current output mode with internal r set section for more explanat ion of the dc crosstalk. 5 efficiency plots in figure 54, figure 55, figure 5 6 , and figure 57 include the i boost quiescent current. ac performance characteristics av dd = v boost_x = 15 v; av ss = ?15 v; dv dd = 2.7 v to 5.5 v; av cc = 4.5 v to 5.5 v; dc-to-dc converter disabled; agnd = dgnd = gndsw x = 0 v; refin = 5 v; voltage outputs: r l = 2 k, c l = 220 pf; current outputs: r l = 300 ; all specifications t min to t max , unless otherwise noted. table 2. parameter 1 min typ max unit test conditions/comments dynamic performance voltage output output voltage settling time 11 s 5 v step to 0.03% fsr, 0 v to 5 v range 18 s 10 v step to 0.03% fsr, 0 v to 10 v range 13 s 100 mv step to 1 lsb (16-bit lsb), 0 v to 10 v range slew rate 1.9 v/s 0 v to 10 v range power-on glitch energy 150 nv-sec digital-to-analog glitch energy 6 nv-sec glitch impulse peak amplitude 25 mv digital feedthrough 1 nv-sec dac to dac crosstalk 2 nv-sec 0 v to 10 v range output noise (0.1 hz to 10 hz bandwidth) 0.15 lsb p-p 16-bit lsb, 0 v to 10 v range output noise spectral density 150 nv/hz measured at 10 khz, midscale output, 0 v to 10 v range ac psrr 83 db 200 mv 50 hz/60 hz sine wave superimposed on power supply voltage
ad5755 rev. 0 | page 8 of 48 parameter 1 min typ max unit test conditions/comments current output output current settling time 15 s to 0.1% fsr (0 ma to 24 ma) see test conditions/ comments ms see figure 48 , figure 49 , and figure 50 output noise (0.1 hz to 10 hz bandwidth) 0.15 lsb p-p 16-bit lsb, 0 ma to 24 ma range output noise spectral density 0.5 na/hz measured at 10 khz, midscale output, 0 ma to 24 ma range 1 guaranteed by design and characterization; not production tested. timing characteristics av dd = v boost_x = 15 v; av ss = ?15 v; dv dd = 2.7 v to 5.5 v; av cc = 4.5 v to 5.5 v; dc-to-dc converter disabled; agnd = dgnd = gndsw x = 0 v; refin = 5 v; voltage outputs: r l = 1 k, c l = 220 pf; current outputs: r l = 300 ; all specifications t min to t max , unless otherwise noted. table 3. parameter 1 , 2 , 3 limit at t min , t max unit description t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 13 ns min 24 th /32 nd sclk falling edge to sync rising edge (see ) figure 77 t 6 198 ns min sync high time t 7 5 ns min data setup time t 8 5 ns min data hold time t 9 20 s min sync rising edge to ldac falling edge (all dacs updated or any channel has digital slew rate control enabled) 5 s min sync rising edge to ldac falling edge (single dac updated) t 10 10 ns min ldac pulse width low t 11 500 ns max ldac falling edge to dac output response time t 12 see the ac performance characteristics section s max dac output settling time t 13 10 ns min clear high time t 14 5 s max clear activation time t 15 40 ns max sclk rising edge to sdo valid t 16 21 s min sync rising edge to dac output response time ( ldac = 0) (all dacs updated) 5 s min sync rising edge to dac output response time ( ldac = 0) (single dac updated) t 17 500 ns min ldac falling edge to sync rising edge t 18 800 ns min reset pulse width t 19 4 20 s min sync high to next sync low (digital slew rate control enabled) (all dacs updated) 5 s min sync high to next sync low (digital slew rate control disabled) (single dac updated) 1 guaranteed by design and characterization; not production tested. 2 all input signals are specified with t rise = t fall = 5 ns (10% to 90% of dv dd ) and timed from a voltage level of 1.2 v. 3 see figure 3, figure 4, figure 5, and figure 6. 4 this specification applies if ldac is held low during the write cycle; otherwise, see t 9 .
ad5755 rev. 0 | page 9 of 48 msb sclk sync sdin ldac ldac = 0 clear 12 24 lsb t 1 v out_x v out_x v out_x t 4 t 6 t 3 t 2 t 5 t 8 t 7 t 10 t 9 t 10 t 11 t 12 t 12 t 16 t 19 t 17 t 13 reset t 18 t 14 07304-002 figure 3. serial interface timing diagram sync msb msb lsb lsb input word specifies register to be read nop condition t 6 t 15 sdin msb msb lsb lsb undefinded selected register data clocked out sdo sclk 24 24 1 1 07304-003 figure 4. readback timing diagram
ad5755 rev. 0 | page 10 of 48 sdo disabled r/w sdin sclk s ync sdo 12 msb dut_ ad1 sdo_ enab dut_ ad0 x x x db15 db14 db1 db0 status status status status 07304-004 figure 5. status readback during write 200a i ol 200a i oh v oh (min) or v ol (max) to output pin c l 50pf 07304-005 figure 6. load circuit for sdo timing diagram
ad5755 rev. 0 | page 11 of 48 absolute maximum ratings t a = 25c, unless otherwise noted. transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4. parameter rating av dd , v boost_x to agnd, dgnd ?0.3 v to +33 v av ss to agnd, dgnd +0.3 v to ?28 v av dd to av ss ?0.3 v to +60 v av cc to agnd ?0.3 v to +7 v dv dd to dgnd ?0.3 v to +7 v digital inputs to dgnd ?0.3 v to dv dd + 0.3 v or +7 v (whichever is less) digital outputs to dgnd ?0.3 v to dv dd + 0.3 v or +7 v (whichever is less) refin, refout to agnd ?0.3 v to av dd + 0.3 v or +7 v (whichever is less) v out_x to agnd av ss to v boost_x or 33 v if using the dc-to-dc circuitry +v sense_x , ?v sense_x to agnd av ss to v boost_x or 33 v if using the dc-to-dc circuitry i out_x to agnd av ss to v boost_x or 33 v if using the dc-to-dc circuitry sw x to agnd ?0.3 to +33 v agnd, gndsw x to dgnd ?0.3 v to +0.3 v operating temperature range (t a ) industrial 1 ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) 125c 64-lead lfcsp ja thermal impedance 2 20c/w power dissipation (t j max ? t a )/ ja lead temperature jedec industry standard soldering j-std-020 esd caution 1 power dissipated on chip must be derated to keep the junction temperature below 125c. 2 based on a jedec 4-layer test board.
ad5755 rev. 0 | page 12 of 48 pin configuration and fu nction descriptions 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 poc reset av dd comp lv_a ?v sense_a +v sense_a comp dcdc_a v boost_a v out_a i out_a av ss comp lv_b ?v sense_b +v sense_b v out_b comp dcdc_b 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 r set_c r set_d refout refin comp lv_d ?v sense_d +v sense_d comp dcdc_d v boost_d v out_d i out_d av ss comp lv_c ?v sense_c +v sense_c v out_c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 r set_b r set_a refgnd refgnd ad0 ad1 sync sclk sdin sdo dv dd dgnd ldac clear alert fault comp dcdc_c i out_c v boost_c av cc sw c gndsw c gndsw d sw d av ss sw a gndsw a gndsw b sw b agnd v boost_b i out_b 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ad5755 top view (not to scale) pin 1 indicator notes 1. this exposed paddle should be connected to the potentialof the av ss pin, or, alternatively, it can be left electrically unconnected. it is recommended that the paddle be thermally connected to a copper plane for en hanced thermal performance. 07304-006 figure 7. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 r set_b an external, precision, low drift 15 k current setting re sistor can be connected to this pin to improve the i out_b temperature drift performance. see the device features section. 2 r set_a an external, precision, low drift 15 k current setting re sistor can be connected to this pin to improve the i out_a temperature drift performance. see the device features section. 3 refgnd ground reference point for internal reference. 4 refgnd ground reference point for internal reference. 5 ad0 address decode for the device under test (dut) on the board. 6 ad1 address decode for the dut on the board. 7 sync active low input. this is the frame synchronization signal for the serial interface. while sync is low, data is transferred in on the falling edge of sclk. 8 sclk serial clock input. data is clocked into the input shift register on the rising edge of sclk. this operates at clock speeds of up to 30 mhz. 9 sdin serial data input. data must be valid on the falling edge of sclk. 10 sdo serial data output. used to clock data from the serial register in readback mode. see figure 4 and figure 5 . 11 dv dd digital supply. the voltage range is from 2.7 v to 5.5 v. 12 dgnd digital ground. 13 ldac load dac, active low input. this is used to update the dac register and consequently the dac outputs. when tied permanently low, the addressed dac data register is updated on the rising edge of sync . if ldac is held high during the write cycle, the dac input register is updated, but the dac output update only takes place at the falling edge of ldac (see ). using this mode, all analog outputs can be updated simultaneously. the figure 3 ldac pin must not be left unconnected. 14 clear active high, edge sensitive input. asserting this pin sets the output current and voltage to the preprogrammed clear code bit setting. only channels enabled to be cleared are cleared. see the device features section for more information. when clear is active, the dac output register cannot be written to.
ad5755 rev. 0 | page 13 of 48 pin no. mnemonic description 15 alert active high output. this pin is asserted when there has been no spi activity on the interface pins for a predetermined time. see the device features section for more information. 16 fault active low output. this pin is asserted low when an open circuit in current mode is detected, a short circuit in voltage mode is detected, a pec error is detect ed, or an overtemperature is detected (see the device features section). open-drain output. 17 poc power-on condition. this pin determines the power-on cond ition and is read during power-on or, alternatively, after a device reset. if poc = 0, the device is powered up with the voltage and current channels in tristate mode. if poc = 1, the device is powered up with a 30 k pull- down resistor to ground on the voltage output channel, and the current channel is in tristate mode. 18 reset hardware reset, active low input. 19 av dd positive analog supply. the voltage range is from 9 v to 33 v. 20 comp lv_a optional compensation capacitor connection for v out_a output buffer. connecting a 220 pf capacitor between this pin and the v out_a pin allows the voltage output to drive up to 2 f. note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. 21 ?v sense_a sense connection for the negative voltage output load connection for v out_a . this pin must stay within 3.0 v of agnd for specified operation. 22 +v sense_a sense connection for the positive voltage output load connection for v out_a . 23 comp dcdc_a dc-to-dc compensation capacitor. conne ct a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of the channel a dc-to-dc converter. altern atively, if using an external compensation resistor, place a resistor in series with a capa citor to ground from this pin (see the dc-to-dc converter compensation capacitors and the aicc supply requirementsslewing sections in the device features section for more information). 24 v boost_a supply for channel a current output stage (see figure 72 ). this is also the supply for the v out_x stage, which is regulated to 15 v by the dc-to-dc converter. to use th e dc-to-dc feature of the device, connect as shown in figure 78 . 25 v out_a buffered analog output voltage for dac channel a. 26 i out_a current output pin for dac channel a. 27 av ss negative analog supply pin. voltag e range is from ?10.8 v to ?26.4 v. 28 comp lv_b optional compensation capacitor connection for v out_b output buffer. connecting a 220 pf capacitor between this pin and the v out_b pin allows the voltage output to drive up to 2 f. note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. 29 ?v sense_b sense connection for the negative voltage output load connection for v out_b . this pin must stay within 3.0 v of agnd for specified operation. 30 +v sense_b sense connection for the positive voltage output load connection for v out_b . 31 v out_b buffered analog output voltage for dac channel b. 32 comp dcdc_b dc-to-dc compensation capacitor. conne ct a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of the channel b dc-to-dc converter. altern atively, if using an external compensation resistor, place a resistor in series with a capa citor to ground from this pin (see the dc-to-dc converter compensation capacitors and the aicc supply requirementsslewing sections in the device features section for more information). 33 i out_b current output pin for dac channel b. 34 v boost_b supply for channel b current output stage (see figure 72 ). this is also the supply for the v out_x stage, which is regulated to 15 v by the dc-to-dc converter. to use th e dc-to-dc feature of the device, connect as shown in figure 78 . 35 agnd ground reference point for analog circuitry. this must be connected to 0 v. 36 sw b switching output for channel b dc-to-dc circuitry. to us e the dc-to-dc feature of the device, connect as shown in figure 78 . 37 gndsw b ground connection for dc-to-dc switching circuit. this pin should always be connected to ground. 38 gndsw a ground connection for dc-to-dc switching circuit. this pin should always be connected to ground. 39 sw a switching output for channel a dc-to-dc circuitry. to us e the dc-to-dc feature of the device, connect as shown in figure 78 . 40 av ss negative analog supply pin. the voltage range is from ? 10.8 v to ?26.4 v. this pin can be connected to 0 v if using the device in unipolar supply mode. 41 sw d switching output for channel d dc-to-dc circuitry. to us e the dc-to-dc feature of the device, connect as shown in figure 78 . 42 gndsw d ground connections for dc-to-dc switching circuit. this pin should always be connected to ground. 43 gndsw c ground connections for dc-to-dc switching circuit. this pin should always be connected to ground.
ad5755 rev. 0 | page 14 of 48 pin no. mnemonic description 44 sw c switching output for channel c dc-to-dc circuitry. to us e the dc-to-dc feature of the device, connect as shown in figure 78 . 45 av cc supply for dc-to-dc circuitry. 46 v boost_c supply for channel c current output stage (see figure 72 ). this is also the supply for the v out_x stage, which is regulated to 15 v by the dc-to-dc converter. to use th e dc-to-dc feature of the device, connect as shown in figure 78 . 47 i out_c current output pin for dac channel c. 48 comp dcdc_c dc-to-dc compensation capacitor. conne ct a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of the channel c dc-to-dc converter. altern atively, if using an external compensation resistor, place a resistor in series with a capa citor to ground from this pin (see the dc-to-dc converter compensation capacitors and aicc supply requirementsslewing sections in the device features section for more information). 49 v out_c buffered analog output voltage for dac channel c. 50 +v sense_c sense connection for the positive voltage output load connection for v out_c . 51 ?v sense_c sense connection for the negative voltage output load connection for v out_c . this pin must stay within 3.0 v of agnd for specified operation. 52 comp lv_c optional compensation capacitor connection for v out_c output buffer. connecting a 220 pf capacitor between this pin and the v out_c pin allows the voltage output to drive up to 2 f. note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. 53 av ss negative analog supply pin. 54 i out_d current output pin for dac channel d. 55 v out_d buffered analog output voltage for dac channel d. 56 v boost_d supply for channel d current output stage (see figure 72 ). this is also the supply for the v out_x stage, which is regulated to 15 v by the dc-to-dc converter. to use th e dc-to-dc feature of the device, connect as shown in figure 78 . 57 comp dcdc_d dc-to-dc compensation capacitor. conne ct a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of channel d dc-to-dc converter. alternativel y, if using an external compensation resistor, place a resistor in series with a capacito r to ground from this pin (see the dc-to-dc converter compensation capacitors and aicc supply requirementsslewing sections in the device features section for more information). 58 +v sense_d sense connection for the positive voltage output load connection for v out_d . 59 ?v sense_d sense connection for the negative voltage output load connection for v out_d . this pin must stay within 3.0 v of agnd for specified operation. 60 comp lv_d optional compensation capacitor connection for v out_d output buffer. connecting a 220 pf capacitor between this pin and the v out_d pin allows the voltage output to drive up to 2 f. note that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. 61 refin external reference voltage input. 62 refout internal reference voltage output. it is recommended to place a 0.1 f capacitor between refout and refgnd. 63 r set_d an external, precision, low drift 15 k current setting re sistor can be connected to this pin to improve the i out_d temperature drift performance. see the device features section. 64 r set_c an external, precision, low drift 15 k current setting re sistor can be connected to this pin to improve the i out_c temperature drift performance. see the device features section. epad exposed pad. this exposed pad should be connected to the potential of the av ss pin, or, alternatively, it can be left electrically unconnected. it is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance.
ad5755 rev. 0 | page 15 of 48 typical performance characteristics voltage outputs 0.0015 0.0010 0.0005 0 ?0.0005 ?0.0010 0 10k 20k 30k 40k 50k 60k inl error (%fsr) code 10v range 5v range +10v range +5v range +10v range with dcdc avdd = +15v avss = ?15v t a = 25c 07304-023 figure 8. integral nonlinearity error vs. dac code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 10k 20k 30k 40k 50k 60k dnl error (lsb) code 10v range 5v range +10v range +5v range +10v range with dcdc av dd = +15v av ss = ?15v t a = 25c 07304-024 figure 9. differential nonlinearity error vs. dac code 10k 20k 30k 40k 50k 60k ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0 total unadjusted error (%fsr) code 10v range 5v range +10v range +5v range +10v range with dcdc av dd = +15v av ss = ?15v t a = 25c 07304-025 figure 10. total unadjusted error vs. dac code ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 ?40 ?20 0 20 40 60 80 100 inl (%fsr) temperature (c) +5v range max inl +10v range max inl 5v range max inl 10v range max inl +5v range min inl +10v range min inl 5v range min inl 10v range min inl av dd = +15v av ss = ?15v output unloaded 07304-127 figure 11. integral nonlinearity error vs. temperature ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 ?40 ?20 0 20 40 60 80 100 dnl error (%fsr) temperature (c) av dd = +15v av ss = ?15v all ranges dnl error max dnl error min 07304-128 figure 12. differential nonlinearity error vs. temperature ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 0.012 ?40 ?20 0 20 40 60 80 100 total unadjusted error (%fsr) temperature (c) av dd = +15v av ss = ?15v output unloaded +5v range +10v range 5v range 10v range 07304-129 figure 13. total unadjusted error vs. temperature
ad5755 rev. 0 | page 16 of 48 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 0.012 ?40 ?20 0 20 40 60 80 100 full-scale error (%fsr) temperature (c) av dd = +15v av ss = ?15v output unloaded +5v range +10v range 5v range 10v range 07304-132 figure 14. full-scale error vs. temperature ?0.0025 ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 ?40 ?20 0 20 40 60 80 100 offset (%fsr) temperature (c) av dd = +15v av ss = ?15v output unloaded +5v range +10v range 07304-133 figure 15. offset error vs. temperature ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 0.0020 0.0025 ?40 ?20 0 20 40 60 80 100 bipolar zero error (%fsr) temperature (c) av dd = +15v av ss = ?15v output unloaded 5v range 10v range 07304-134 figure 16. bipolar zero error vs. temperature ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 ?40 ?20 0 20 40 60 80 100 temperature (c) av dd = +15v av ss = ?15v output unloaded +5v range +10v range 5v range 10v range gain error (%fsr) 07304-135 figure 17. gain error vs. temperature ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 zero-scale error (%fsr) av dd = +15v av ss = ?15v output unloaded +5v range +10v range 5v range 10v range ?40 ?20 0 20 40 60 80 100 temperature (c) 07304-136 figure 18. zero-scale error vs. temperature 0.0020 ?0.0020 10 15 20 25 30 inl eror (%fsr) supply (v) 07304-034 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 0v to 10v range max inl 0v to 10v range min inl t a = 25c av ss = ?26.4v for av dd > +26.4v figure 19. integral nonlinearity error vs. av dd /|av ss |
ad5755 rev. 0 | page 17 of 48 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 10 15 20 25 30 dnl error (%fsr) supply (v) av ss = ?26.4v for av dd > +26.4v av dd = +15v av ss = ?15v all ranges t a = 25c dnl error max dnl error min 07304-138 figure 20. differential nonlinearity error vs. av dd /|av ss | 0.008 0.006 0.004 0.002 0 ?0.008 ?0.004 10 15 20 25 30 total unadjusted error (%fsr) supply (v) 0v to 10v range max inl 0v to 10v range min inl t a = 25c av ss = ?26.4v for av dd > +26.4v 07304-035 figure 21. total unadjusted error vs. av dd /|av ss | 0.0020 0.0015 0.0010 0.0005 0 ?0.0005 ?0.0010 ?0.0015 ?0.0020 ?20 201612 840 ?4 ?8?12?16 output voltage delta (v) output current (ma) 8ma limit, code = 0xffff 16ma limit, code = 0xffff av dd = +15v av ss = ?15v 10v range t a = 25c 07304-036 figure 22. source and sink capability of output amplifier 12 8 4 0 ?4 ?8 ?12 ?5 15 10 5 0 output voltage (v) time (s) av dd = +15v av ss = ?15v 10v range t a = 25c output unloaded 07304-037 figure 23. full-scale positive step 12 8 4 0 ?4 ?8 ?12 ?5 15 10 5 0 output voltage (v) time (s) av dd = +15v av ss = ?15v 10v range t a = 25c output unloaded 07304-038 figure 24. full-scale negative step 15 10 5 0 ?5 ?10 ?15 ?20 05 4 3 2 1 output voltage (v) time (s) 0x7fff to 0x8000 0x8000 to 0x7fff av dd = +15v av ss = ?15v +10v range t a = 25oc 07304-039 figure 25. digital-to-analog glitch
ad5755 rev. 0 | page 18 of 48 15 10 5 0 ?5 ?10 ?15 07 56 1234 output voltage (v) time (s) 8 9 1 0 av dd = +15v av ss = ?15v 10v range t a = 25c output unloaded 07304-040 60 40 20 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 024681 output voltage (mv) time (s) 0 poc = 1 poc = 0 av dd = +15v av ss = ?15v 10v range t a = 25c int_enable = 1 07304-044 figure 29. v out_x vs. time on output enable figure 26. peak-to-peak noise (0.1 hz to 10 hz bandwidth) 0 ?120 ?100 ?80 ?60 ?40 ?20 10 100 1k 10k 100k 1m 10m v out_x psrr (db) frequency (hz) av dd = +15v v boost = +15v av ss = ?15v t a = 25c 07304-045 300 200 100 0 ?100 ?200 ?300 0 78910 56 1234 output voltage (v) time (s) av dd = +15v av ss = ?15v 10v range t a = 25c output unloaded 07304-041 figure 30. v out_x psrr vs. frequency figure 27. peak-to-peak noise (100 khz bandwidth) 25 20 15 10 5 0 ?5 ?10 ?15 ?20 ?25 0 255075100125 output voltage (mv) time (s) av dd = +15v av ss = ?15v t a = 25c 07304-043 figure 28. v out_x vs. time on power-up
ad5755 rev. 0 | page 19 of 48 current outputs ?0.0025 ?0.0015 ?0.0005 0.0005 0.0015 0.0025 0 10000 20000 30000 40000 50000 60000 inl error (%fsr) code av dd = +15v av ss = ?15v t a = 25c 4ma to 20ma, external r set 4ma to 20ma, external r set , with dc-to-dc converter 4ma to 20ma, internal r set 4ma to 20ma, internal r set , with dc-to-dc converter 07304-149 figure 31. integral nonlinearity vs. code 0 10000 20000 30000 40000 50000 60000 dnl error (lsb) code av dd = +15v av ss = ?15v t a = 25c ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 07304-150 4ma to 20ma, external r set 4ma to 20ma, external r set , with dc-to-dc converter 4ma to 20ma, internal r set 4ma to 20ma, internal r set , with dc-to-dc converter figure 32. differential nonlinearity vs. code 0 10000 20000 30000 40000 50000 60000 total unadjusted error (%fsr) code ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 0.025 0.030 0.035 av dd = +15v av ss = ?15v t a = 25c all channels enabled 4ma to 20ma, external r set 4ma to 20ma, external r set , with dc-to-dc converter 4ma to 20ma, internal r set 4ma to 20ma, internal r set , with dc-to-dc converter 07304-151 figure 33. total unadjusted error vs. code ?0.0010 ?0.0008 ?0.0006 ?0.0004 ?0.0002 0 0.0002 0.0004 0.0006 0.0008 0.0010 integr a l nonlineari t y error (%fsr) 4ma to 20ma range max inl 0ma to 20ma range max inl 0ma to 24ma range max inl 4ma to 20ma range max inl 0ma to 24ma range min inl 0ma to 20ma range min inl av dd = +15v av ss = ?15v ?40 ?20 0 20 40 60 80 100 temperature (c) 07304-152 figure 34. integral nonlinearity vs. temperature, internal r set ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 0.0020 integral nonlinearity error (%fsr) 4ma to 20ma range max inl 0ma to 20ma range max inl 0ma to 24ma range max inl 4ma to 20ma range min inl 0ma to 24ma range min inl 0ma to 20ma range min inl ?40 ?20 0 20 40 60 80 100 temperature (c) av dd = +15v av ss = ?15v 07304-153 figure 35. integral nonlinearity vs. temperature, external r set ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 ?40 ?20 0 20 40 60 80 100 differenti a l nonlinearity error (%fsr) temperature (c) av dd = +15v av ss = ?15v all ranges internal and external r set dnl error max dnl error min 07304-154 figure 36. differential nonlinearity vs. temperature
ad5755 rev. 0 | page 20 of 48 ?0.08 ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 total unadjsuted error (%fsr) ?40 ?20 0 20 40 60 80 100 temperature (c) av dd = +15v av ss = ?15v 4ma to 20ma internal r set 4ma to 20ma external r set 0ma to 20ma internal r set 0ma to 20ma external r set 0ma to 24ma external r set 0ma to 24ma internal r set 07304-155 figure 37. total unadjusted error vs. temperature ?0.08 ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 full-scale error (%fsr) ?40 ?20 0 20 40 60 80 100 temperature (c) av dd = +15v av ss = ?15v 4ma to 20ma internal r set 4ma to 20ma external r set 0ma to 20ma internal r set 0ma to 20ma external r set 0ma to 24ma external r set 0ma to 24ma internal r set 07304-157 figure 38. full-scale error vs. temperature ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 offset error (%fsr) ?40 ?20 0 20 40 60 80 100 temperature (c) 4ma to 20ma internal r set 4ma to 20ma external r set 0ma to 20ma internal r set 0ma to 20ma external r set 0ma to 24ma external r set 0ma to 24ma internal r set av dd = +15v av ss = ?15v 07304-158 figure 39. offset error vs. temperature ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 gain error (%fsr) ?40 ?20 0 20 40 60 80 100 temperature (c) 4ma to 20ma internal r set 4ma to 20ma external r set 0ma to 20ma internal r set 0ma to 20ma external r set 0ma to 24ma external r set 0ma to 24ma internal r set av dd = +15v av ss = ?15v 07304-159 figure 40. gain error vs. temperature ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 0.0020 0.0025 10 15 20 25 30 inl error (%fsr) supply (v) 4ma to 20ma range max inl 4ma to 20ma range min inl t a = 25c av ss = ?26.4v for av dd > +26.4v 07304-056 figure 41. integral nonlinearity error vs. av dd /|av ss |, over supply, external r set ?0.0020 ?0.0025 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 10 15 20 25 30 inl error (%fsr) supply (v) 4ma to 20ma range max inl 4ma to 20ma range min inl t a = 25c av ss = ?26.4v for av dd > +26.4v 07304-057 figure 42. integral nonlinearity error vs. av dd /|av ss |, over supply, internal r set
ad5755 rev. 0 | page 21 of 48 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 10 15 20 25 30 differential nonlinearity error (%fsr) supply (v) dnl error max dnl error min av ss = ?15v for av dd > +26.4v all ranges internal and external r set t a = 25c 07304-162 figure 43. differential nonlinearity error vs. av dd 0 0.002 0.004 0.006 0.008 0.010 0.012 10 15 20 25 30 total unadjusted erro r (%fsr) supply (v) 4ma to 20ma range max tue 4ma to 20ma range min tue t a = 25c av ss = ?26.4v for av dd > +26.4v 07304-060 figure 44. total unadjusted error vs. av dd , external r set 10 15 20 25 30 total unadjusted error (%fsr) supply (v) 4ma to 20ma range max tue 4ma to 20ma range min tue t a = 25c av ss = ?26.4v for av dd > +26.4v ?0.020 ?0.018 ?0.016 ?0.014 ?0.012 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 07304-061 figure 45. total unadjusted error vs. av dd , internal r set 6 5 4 3 2 1 0 02 15 10 5 current (a) time (s) 0 av dd = +15v av ss = ?15v t a = 25c r load = 300 ? 07304-062 figure 46. output current vs. time on power-up 4 ?10 ?8 ?6 ?4 ?2 0 2 0123456 current (a) time (s) av dd = +15v av ss = ?15v t a = 25c r load = 300 ? int_en = 1 07304-063 figure 47. output current vs . time on output enable 0 5 10 15 20 25 30 output current (ma) ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 time (ms) 0ma to 24ma range 1k ? load f sw = 410khz inductor = 10h (xal4040-103) av cc = 5v t a = 25c i out v boost 07304-167 figure 48. output current and v boost_x settling with dc-to-dc converter (see figure 78 )
ad5755 rev. 0 | page 22 of 48 0 5 10 15 20 25 30 output current (ma) ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 time (ms) i out , t a = ?40c i out , t a = +25c i out , t a = +105c 0ma to 24ma range 1k ? load f sw = 410khz inductor = 10h (xal4040-103) av cc = 5v 07304-168 figure 49. output current settling wi th dc-to-dc converter vs. time and temperature (see figure 78 ) 0 5 10 15 20 25 30 output current (ma) ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 time (ms) i out , av cc = 4.5v i out , av cc = 5.0v i out , av cc = 5.5v 0ma to 24ma range 1k ? load f sw = 410khz inductor = 10h (xal4040-103) t a = 25c 07304-169 figure 50. output current settling wi th dc-to-dc converter vs. time and av cc (see figure 78 ) ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 02468101214 current (ac-coupled) (a) time (s) av cc = 5v f sw = 410khz inductor = 10h (xal4040-103) 0ma to 24ma range 1k? load external r set t a = 25c 20ma output 10ma output 07304-170 figure 51. output current vs. time with dc-to-dc converter (see figure 78 ) 8 7 6 5 4 3 2 1 0 0 5 10 15 20 headroom voltage (v) current (ma) 07304-067 0ma to 24ma range 1k? load f sw = 410khz inductor = 10h (xal4040-103) t a = 25c figure 52. dc-to-dc converter headroom vs. output current (see figure 78 ) 0 ?120 ?100 ?80 ?60 ?40 ?20 10 100 1k 10k 100k 1m 10m i out_x psrr (db) frequency (hz) av dd = +15v v boost = +15v av ss = ?15v t a = 25c 07304-068 figure 53. i out_x psrr vs. frequency
ad5755 rev. 0 | page 23 of 48 dc-to-dc block 90 85 80 75 70 65 60 55 50 02 20 16 12 8 4 v boost_x efficiency (%) current (ma) 4 0ma to 24ma range 1k ? load external r set f sw = 410khz inductor = 10h (xal4040-103) t a = 25c av cc = 4.5v av cc = 5v av cc = 5.5v 07304-016 figure 54. efficiency at v boost_x vs. output current (see figure 78 ) 90 85 80 75 70 65 60 55 50 ?40 100 40 60 80 20 0 ?20 v boost efficiency (%) current (ma) 0ma to 24ma range 1k? load external r set av cc = 5v f sw = 410khz inductor = 10h (xal4040-103) t a = 25c 20ma 07304-017 figure 55. efficiency at v boost_x vs. temperature (see figure 78 ) 80 70 60 50 40 30 20 02 20 16 12 8 4 i out_x efficiency (%) current (ma) 07304-018 4 0ma to 24ma range 1k? load external r set f sw = 410khz inductor = 10h (xal4040-103) t a = 25c av cc = 4.5v av cc = 5v av cc = 5.5v figure 56. output efficiency vs. output current (see figure 78 ) 80 70 60 50 40 30 20 ?40 100 40 60 80 20 0 ?20 i out_x efficiency (%) current (ma) 0ma to 24ma range 1k ? load external r set av cc = 5v f sw = 410 khz inductor = 10h (xal4040-103) 20ma 07304-019 figure 57. output efficiency vs. temperature (see figu re 78 ) 0 0.1 0.2 0.3 0.4 0.5 0.6 ?40 ?20 0 20 40 60 80 100 switch resistance ( ? ) temperature (c) 07304-123 figure 58. switch resistance vs. temperature
ad5755 rev. 0 | page 24 of 48 reference 16 14 12 10 8 6 4 2 0 ?2 0 0.2 0.4 0.6 0.8 1.0 1.2 voltage (v) time (ms) av dd ref out t a = 25c 07304-010 figure 59. refout turn-on transient 4 3 2 1 0 ?1 ?2 ?3 0246 81 reference output voltage (v) time (s) 0 av dd = 15v t a = 25c 07304-011 figure 60. refout output noise (0 .1 hz to 10 hz bandwidth) 150 100 50 0 ?50 ?100 ?150 0 5 10 15 20 reference output voltage (v) time (ms) av dd = 15v t a = 25c 07304-012 figure 61. refout output no ise (100 khz bandwidth) 5.0000 5.0005 5.0010 5.0015 5.0020 5.0025 5.0030 5.0035 5.0040 5.0045 5.0050 ?40 ?20 0 20 40 60 80 100 reference output voltage (v) temperature (c) 30 devices shown av dd = 15v 07304-163 figure 62. refout vs. temperature (when the ad5755 is soldered onto a pcb, the reference shifts due to thermal shock on the package. the average output voltage shift is ?4 mv. measur ement of these parts after seven days shows that the outputs typically shift back 2 mv toward their initial values. this second shift is due to the relaxation of stress incurred during soldering.) 5.002 5.001 5.000 4.999 4.998 4.997 4.996 4.995 024681 0 reference output voltage (v) load current (ma) 07304-014 av dd = 15v t a = 25c figure 63. refout vs. load current 5.00000 4.99995 4.99990 4.99980 4.99985 4.99975 4.99970 4.99965 4.99960 10 15 20 25 30 reference output voltage (v) av dd (v) t a = 25c 07304-015 figure 64. refout vs. supply
ad5755 rev. 0 | page 25 of 48 5 general 450 400 350 300 250 200 150 100 50 0 0123 4 di cc (a) sdin voltage (v) dv cc = 5v t a = 25c 07304-007 figure 65. di cc vs. logic input voltage 10 8 6 4 2 0 ?12 ?10 ?8 ?6 ?4 ?2 10 15 20 25 30 current (ma) voltage (v) ai dd ai ss t a = 25c v out = 0v output unloaded 07304-008 figure 66. ai dd /ai ss vs. av dd /|av ss | 8 7 0 1 2 3 4 5 6 current (ma) voltage (v) ai dd t a = 25c i out = 0ma 10 15 20 25 30 07304-009 figure 67. ai dd vs. av dd 13.4 13.3 13.2 13.1 13.0 12.9 12.8 12.7 12.6 ?40?200 20406080100 frequency (mhz) temperature (c) dv cc = 5.5v 07304-020 figure 68. internal oscillator frequency vs. temperature 14.4 14.2 14.0 13.8 13.6 13.4 13.2 13.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 frequency (mhz) voltage (v) dv cc = 5.5v t a = 25c 07304-021 figure 69. internal oscillator frequency vs. dv cc supply voltage
ad5755 rev. 0 | page 26 of 48 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation, in lsbs, from the best fit line through the dac transfer function. a typical inl vs. code plot is shown in figure 8 . differential nonlinearity (dnl) differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot is shown in figure 9 . monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital input code. the ad5755 is monotonic over its full operating temperature range. negative full-scale error/zero-scale error negative full-scale error is the error in the dac output voltage when 0x0000 (straight binary coding) is loaded to the dac register. zero-scale tc this is a measure of the change in zero-scale error with a change in temperature. zero-scale error tc is expressed in ppm fsr/c. bipolar zero error bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 v when the dac register is loaded with 0x8000 (straight binary coding). bipolar zero tc bipolar zero tc is a measure of the change in the bipolar zero error with a change in temperature. it is expressed in ppm fsr/c. offset error in voltage output mode, offset error is the deviation of the analog output from the ideal quarter-scale output when in bipolar output ranges and the dac register is loaded with 0x4000 (straight binary coding). in current output mode, offset error is the deviation of the analog output from the ideal zero-scale output when all dac registers are loaded with 0x0000. gain error this is a measure of the span error of the dac. it is the devia- tion in slope of the dac transfer characteristic from the ideal, expressed in % fsr. gain tc this is a measure of the change in gain error with changes in temperature. gain tc is expressed in ppm fsr/c. full-scale error full-scale error is a measure of the output error when full-scale code is loaded to the dac register. ideally, the output should be full-scale ? 1 lsb. full-scale error is expressed in percent of full-scale range (% fsr). full-scale tc full-scale tc is a measure of the change in full-scale error with changes in temperature and is expressed in ppm fsr/c. tot a l un a dju s te d e r ror total unadjusted error (tue) is a measure of the output error taking all the various errors into account, including inl error, offset error, gain error, temperature, and time. tue is expressed in % fsr. dc crosstalk this is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac while monitoring another dac, which is at midscale. current loop compliance voltage the maximum voltage at the i out_x pin for which the output current is equal to the programmed value. voltage reference thermal hysteresis voltage reference thermal hysteresis is the difference in output voltage measured at +25c compared to the output voltage measured at +25c after cycling the temperature from +25c to ?40c to +105c and back to +25c. the hysteresis is specified for the first and second temperature cycles and is expressed in ppm. output voltage settling time output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. plots of settling time are shown in figure 23 , figure 49 , and figure 50 . slew rate the slew rate of a device is a limitation in the rate of change of the output voltage. the output slewing speed of a voltage- output digital-to-analog converter is usually limited by the slew rate of the amplifier used at its output. slew rate is measured from 10% to 90% of the output signal and is given in v/s. power-on glitch energy power-on glitch energy is the impulse injected into the analog output when the ad5755 is powered on. it is specified as the area of the glitch in nv-sec. see figure 28 and figure 46 . digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state, but the output voltage remains constant. it is normally specified as the area of the glitch in nv-sec and is measured when the digital input code is changed by 1 lsb at the major carry transition (~0x7fff to 0x8000). see figure 25 .
ad5755 rev. 0 | page 27 of 48 glitch impulse peak amplitude glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the dac register changes state. it is specified as the amplitude of the glitch in mv and is measured when the digital input code is changed by 1 lsb at the major carry transition (~0x7fff to 0x8000). see figure 25 . digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not updated. it is specified in nv-sec and measured with a full-scale code change on the data bus. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and a subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with ldac low and monitoring the output of another dac. the energy of the glitch is expressed in nv-sec. power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the power supply voltage. reference tc reference tc is a measure of the change in the reference output voltage with a change in temperature. it is expressed in ppm/c. line regulation line regulation is the change in reference output voltage due to a specified change in supply voltage. it is expressed in ppm/v. load regulation load regulation is the change in reference output voltage due to a specified change in load current. it is expressed in ppm/ma. dc-to-dc converter headroom this is the difference between the voltage required at the current output and the voltage supplied by the dc-to-dc converter. see figure 52 . output efficiency cc cc load aiav ri out 2 this is defined as the power delivered to a channels load vs. the power delivered to the channels dc-to-dc input. efficiency at v boost_x cc cc xboost out aiav v i _ this is defined as the power delivered to a channels v boost_x supply vs. the power delivered to the channels dc-to-dc input. the v boost_x quiescent current is considered part of the dc-to- dc converters losses.
ad5755 rev. 0 | page 28 of 48 theory of operation the ad5755 is a quad, precision digital-to-current loop and voltage output converter designed to meet the requirements of industrial process control applications. it provides a high precision, fully integrated, low cost, single-chip solution for generating current loop and unipolar/bipolar voltage outputs. the current ranges available are 0 ma to 20 ma, 0 ma to 24 ma, and 4 ma to 20 ma. the voltage ranges available are 0 v to 5 v, 5 v, 0 v to 10 v, and 10 v. the current and voltage outputs are available on separate pins, and only one is active at any one time. the desired output configuration is user selectable via the dac control register. on-chip dynamic power control minimizes package power dissipation in current mode. dac architecture the dac core architecture of the ad5755 consists of two matched dac sections. a simplified circuit diagram is shown in figure 70 . the four msbs of the 16-bit data-word are decoded to drive 15 switches, e1 to e15. each of these switches connects one of 15 matched resistors to either ground or the reference buffer output. the remaining 12 bits of the data-word drive switch s0 to switch s11 of a 12-bit voltage mode r-2r ladder network. 8-/12-bit r-2r ladder four msbs decoded into 15 equal segments 2r 2r s0 s1 s7/s11 e1 e2 e15 v out 2r 2r 2r 2r 2r 07304-069 figure 70. dac ladder structure the voltage output from the dac core is either converted to a current (see figure 72 ), which is then mirrored to the supply rail so that the application simply sees a current source output, or it is buffered and scaled to output a software selectable unipolar or bipolar voltage range (see figure 71 ). both the voltage and current outputs are supplied by v boost_x . the current and voltage are output on separate pins and cannot be output simultaneously. a channels current and voltage output pins can be tied together. range scaling dac v out_x short fault +v sense_x ?v sense_x v out_x 07304-070 figure 71. voltage output 16-bit dac v boost_x r2 t2 t1 r3 i out_x r set a1 a2 07304-071 figure 72. voltage-to-curre nt conversion circuitry voltage output amplifier the voltage output amplifier is capable of generating both unipolar and bipolar output voltages. it is capable of driving a load of 1 k in parallel with 1 f (with an external compen- sation capacitor) to agnd. the source and sink capabilities of the output amplifier are shown in figure 22 . the slew rate is 1.9 v/s with a full-scale settling time of 16 s (10 v step). if remote sensing of the load is not required, connect +v sense_x directly to v out_x and connect ?v sense directly to agnd. +v sense_x must stay within 3.0 v of v out_x , and ? v sense_x must stay within 3.0 v of agnd for correct operation. driving large capacitive loads the voltage output amplifier is capable of driving capacitive loads of up to 2 f with the addition of a 220 pf nonpolarized compensation capacitor on each channel. care should be taken to choose an appropriate value of compensation capacitor. this capacitor, while allowing the ad5755 to drive higher capacitive loads and reduce overshoot, increases the settling time of the part and, therefore, affects the bandwidth of the system. with- out the compensation capacitor, up to 10 nf capacitive loads can be driven. see table 5 for information on connecting compensation capacitors. reference buffers the ad5755 can operate with either an external or internal reference. the reference input requires a 5 v reference for specified performance. this input voltage is then buffered before it is applied to the dac. power-on state of ad5755 on initial power-up of the ad5755, the power-on reset circuit powers up in a state that is dependent on the power-on condition (poc) pin. if poc = 0, the voltage output and current output channels power up in tristate mode. if poc = 1, the voltage output channel powers up with a 30 k pull-down resistor to ground, and the current output channel powers up to tristate.
ad5755 rev. 0 | page 29 of 48 even though the output ranges are not enabled, the default output range is 0 v to 5 v, and the clear code register is loaded with all zeros. this means that if the user clears the part after power-up, the output is actively driven to 0 v (if the channel has been enabled for clear). serial interface the ad5755 is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 mhz and is compatible with spi, qspi, microwire, and dsp standards. data coding is always straight binary. input shift register the input shift register is 24 bits wide. data is loaded into the device msb first as a 24-bit word under the control of a serial clock input, sclk. data is clocked in on the falling edge of sclk. if packet error checking, or pec (see the device features section), is enabled, an additional eight bits must be written to the ad5755, creating a 32-bit serial interface. there are two ways in which the dac outputs can be updated: individual updating or simultaneous updating of all dacs. individual dac updating in this mode, ldac is held low while data is being clocked into the dac data register. the addressed dac output is updated on the rising edge of sync . see and for timing information. table 3 figure 3 simultaneous updating of all dacs in this mode, ldac is held high while data is being clocked into the dac data register. only the first write to each channels dac data register is valid after ldac is brought high. any subse- quent writes while ldac is still held high are ignored, though they are loaded into the dac data register. all the dac outputs are updated by taking ldac low after sync is taken high. v out_x dac register interface logic output i/v amplifier ldac sdo sdin 16-bit dac v refin sync dac data register offset and gain calibration dac input register sclk 07304-072 figure 73. simplified serial interface of input loading circuitry for one dac channel transfer function table 6 shows the input code to ideal output voltage relationship for the ad5755 for straight binary data coding of the 10 v output range. table 6. ideal output voltage to input code relationship digital input straight binary data coding analog output msb lsb v out 1111 1111 1111 1111 +2 v ref (32,767/32,768) 1111 1111 1111 1110 +2 v ref (32,766/32,768) 1000 0000 0000 0000 0 v 0000 0000 0000 0001 ?2 v ref (32,767/32,768) 0000 0000 0000 0000 ?2 v ref
ad5755 rev. 0 | page 30 of 48 registers table 7 shows an overview of the registers for the ad5755. table 7. data, control, and readback registers for the ad5755 register description data dac data register (4) used to write a dac code to each dac channel. ad5755 data bits = d15 to d0. there are four dac data registers, one per dac channel. gain register (4) used to program gain trim, on a per channel basis. ad5755 data bits = d15 to d0. there are four gain registers, one per dac channel. offset register (4) used to program offset trim, on a per channel basis. ad5755 data bits = d15 to d0. there are four offset registers, one per dac channel. clear code register (4) used to program clear code on a per channel basis. ad5755 data bits = d15 to d0. there are four clear code registers, one per dac channel. control main control register used to configure the part for main operation. sets functions such as status readback during write, enables output on all channels simultaneously, powers on all dc-to-dc converter blocks simultaneously, and enables and sets conditions of the watchdog timer. see the device features section for more details. software register has three functions. used to perform a reset, to toggl e the user bit, and, as part of the watchdog timer feature, to verify correct data communication operation. slew rate control register (4) use to program the slew rate of the output. there are four slew rate control registers, one per channel. dac control register (4) these registers are used to control the following: set the output range, for example, 4 ma to 20 ma, 0 v to 10 v. set whether an internal/external sense resistor is used. enable/disable a channel for clear. enable/disable overrange. enable/disable internal circuitry on a per channel basis. enable/disable output on a per channel basis. power on dc-to-dc converters on a per channel basis. there are four dac control registers, one per dac channel. dc-to-dc control register use to set the dc-to-dc control parameters. can control dc-to-dc maximum voltage, phase, and frequency. readback status register this contains any fault in formation, as well as a user toggle bit.
ad5755 rev. 0 | page 31 of 48 pr ogramming sequence to write/enable the output correctly to correctly write to and set up the part from a power-on condition, use the following sequence: 1. perform a hardware or software reset after initial power-on. 2. the dc-to-dc converter supply block must be configured. set the dc-to-dc switching frequency, maximum output voltage allowed, and the phase that the four dc-to-dc channels clock at. 3. configure the dac control register on a per channel basis. the output range is selected, and the dc-to-dc converter block is enabled (dc_dc bit). other control bits can be configured at this point. set the int_enable bit; however, the output enable bit (outen) should not be set. 4. write the required code to the dac data register. this implements a full dac calibration internally. allow at least 200 s before step 5 for reduced output glitch. 5. write to the dac control register again to enable the output (set the outen bit). a flowchart of this sequence is shown in figure 74 . 07304-073 power on. step 1: perform a software/hardware reset. step 4: write to each/all dac data registers. allow at least 200s between step 3 and step 5 for reduced output glitch. step 2: write to dc-to-dc control register to set dc-to-dc clock frequency, phase, and maximum voltage. step 3: write to dac control register. select the dac channel and output range. set the dc_dc bit and other control bits as required. set the int_enable bit but do not select the outen bit. step 5: write to dac control register. reload sequence as in step 3 above. this time select the outen bit to enable the output. figure 74. programming sequence for enabling the output correctly changing and reprogramming the range when changing between ranges, the same sequence as described in the programming sequence to write/enable the output correctly section should be used. it is recommended to set the range to its zero point (can be midscale or zero scale) prior to disabling the output. because the dc-to-dc switching frequency, maximum voltage, and phase have already been selected, there is no need to reprogram these. a flowchart of this sequence is shown in figure 75 . channel?s output is enabled. step 3: write value to the dac data register. step 1: write to channel?s dac data register. set the output to 0v (zero or midscale). step 2: write to dac control register. disable the output (outen = 0), and set the new output range. keep the dc_dc bit and the int_enable bit set. step 4: write to dac control register. reload sequence as in step 2 above. this time select the outen bit to enable the output. 07304-074 figure 75. steps for changing the output range
ad5755 rev. 0 | page 32 of 48 data registers the input register is 24 bits wide. when pec is enabled, the input register is 32 bits wide, with the last eight bits correspond- ing to the pec code (see the packet error checking section for more information on pec). when writing to a data register, the format in table 8 must be used. dac data register when writing to the ad5755 dac data registers, d15 to d0 are used for dac data bits. tabl e 10 shows the register format and table 9 describes the function of bit d23 to bit d16. table 8. writing to a data register msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 to d0 r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad0 data table 9. input register decode bit description r/ w indicates a read from or a write to the addressed register. dut_ad1, dut_ad0 used in association with the external pins, ad1 and ad 0, to determine which ad5755 device is being addressed by the system controller. dut_ad1 dut_ad0 function 0 0 addresses part with pin ad1 = 0, pin ad0 = 0 0 1 addresses part with pin ad1 = 0, pin ad0 = 1 1 0 addresses part with pin ad1 = 1, pin ad0 = 0 1 1 addresses part with pin ad1 = 1, pin ad0 = 1 dreg2, dreg1, dreg0 selects whether a data register or a control register is writ ten to. if a control register is selected, a further decode of creg bits (see table 17 ) is required to select the particular control register, as follows. dreg2 dreg1 dreg0 function 0 0 0 write to dac data register (individual channel write) 0 1 0 write to gain register 0 1 1 write to gain register (all dacs) 1 0 0 write to offset register 1 0 1 write to offset register (all dacs) 1 1 0 write to clear code register 1 1 1 write to a control register dac_ad1, dac_ad0 these bits are used to decode the dac channel. dac_ad1 dac_ad0 dac channel/register address 0 0 dac a 0 1 dac b 1 0 dac c 1 1 dac d x x these are dont cares if they are not relevant to the operation being performed. table 10. programming the dac data registers msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 to d0 r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad0 dac data
ad5755 rev. 0 | page 33 of 48 gain register the 16-bit gain register, as shown in table 11 , allows the user to adjust the gain of each channel in steps of 1 lsb. this is done by setting the dreg[2:0] bits to 010. it is possible to write the same gain code to all four dac channels at the same time by setting the dreg[2:0] bits to 011. the gain register coding is straight binary as shown in table 12 . the default code in the gain register is 0xffff. in theory, the gain can be tuned across the full range of the output. in practice, the maximum recommended gain trim is about 50% of programmed range to maintain accuracy. see the digital offset and gain control section in the device features section for more information. offset register the 16-bit offset register, as shown in table 13 , allows the user to adjust the offset of each channel by ?32,768 lsbs to +32,767 lsbs in steps of 1 lsb. this is done by setting the dreg[2:0] bits to 100. it is possible to write the same offset code to all four dac channels at the same time by setting the dreg[2:0] bits to 101. the offset register coding is straight binary as shown in table 14 . the default code in the offset register is 0x8000, which results in zero offset programmed to the output. see the digital offset and gain control section in the device features section for more information. clear code register the 16-bit clear code register allows the user to set the clear value of each channel as shown in table 15 . it is possible, via software, to enable or disable on a per channel basis which channels are cleared when the clear pin is activated. the default clear code is 0x0000. see the asynchronous clear section in the device features section for more information. table 11. programming the gain register r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad0 d15 to d0 0 device address 0 1 0 dac channel address gain adjustment table 12. gain register gain adjustment g15 g14 g13 g12 to g4 g3 g2 g1 g0 +65,535 lsbs 1 1 1 1 1 1 1 1 +65,534 lsbs 1 1 1 1 1 1 0 0 1 lsb 0 0 0 0 0 0 0 1 0 lsbs 0 0 0 0 0 0 0 0 table 13. programming the offset register r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad0 d15 to d0 0 device address 1 0 0 dac channel address offset adjustment table 14. offset register options offset adjustment of15 of14 of13 of12 to of4 of3 of2 of1 of0 +32,767 lsbs 1 1 1 1 1 1 1 1 +32,766 lsbs 1 1 1 1 1 1 0 0 no adjustment (default) 1 0 0 0 0 0 0 0 ?32,767 lsbs 0 0 0 0 0 0 0 0 ?32,768 lsbs 0 0 0 0 0 0 0 0 table 15. programming the clear code register r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad0 d15 to d0 0 device address 1 1 0 dac channel address clear code
ad5755 rev. 0 | page 34 of 48 control registers when writing to a control register, the format shown in table 16 must be used. see table 9 for information on the configuration of bit d23 to bit d16. the control registers are addressed by setting the dreg[2:0] bits to 111 and then setting the creg[2:0] bits to the appropriate decode address for that register, according to table 17 . these creg bits select among the various control registers. main control register the main control register options are shown in table 18 and table 19 . see the device features section for more information on the features controlled by the main d o ntrol s egister. table 16. writin g to a control register msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 to d0 r/ w dut_ad1 dut_ad0 1 1 1 dac_ad1 dac_ad0 creg2 creg1 creg0 data table 17. register access decode creg2 (d15) creg1 (d14) creg0 (d13) function 0 0 0 slew rate control register (one per channel) 0 0 1 main control register 0 1 0 dac control register (one per channel) 0 1 1 dc-to-dc control register 1 0 0 software register (one per channel) table 18. programming the main control register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 to d0 0 0 1 poc statread ewd wd1 wd0 x 1 shtcctlim outen_all dcdc_all x 1 1 x = dont care. table 19. main control register functions bit description poc the poc bit determines the state of the voltage output ch annels during normal operation. its default value is 0. poc = 0. the output goes to the value set by the poc hard ware pin when the voltage o utput is not enab led (default). poc = 1. the output goes to the opposite value of the po c hardware pin if the voltage output is not enabled. statread enable status readback during a write. see the device features section. statread = 1, enable. statread = 0, disable (default). ewd enable watchdog timer. see the device features section for more information. ewd = 1, enable watchdog. ewd = 0, disable watchdog (default). wd1, wd0 timeout select bits. used to select the timeout period for the watchdog timer. wd1 wd0 timeout period (ms) 0 0 5 0 1 10 1 0 100 1 1 200 shtcctlim programmable short-circuit limit on the v out_x pin in the event of a short-circuit condition. 0 = 16 ma (default). 1 = 8 ma. outen_all enables the output on all four dacs simultaneously. do not use the outen_all bit when using the outen bit in the dac control register. dcdc_all when set, powers up the dc-to-dc converter on all four channels simultaneously. to power down the dc-to-dc converters, all channel outputs must first be disabled. do not use the dcdc_all bit when using the dc_dc bit in the dac control register.
ad5755 rev. 0 | page 35 of 48 dac control register the dac control register is used to configure each dac channel. the dac control register options are shown in table 20 and table 21 . table 20. programming dac control register d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 x 1 x 1 x 1 x 1 int_enable clr_en outen rset dc_dc ovrng r2 r1 r0 1 x = dont care. table 21. dac control register functions bit description int_enable powers up the dc-to-dc converter, dac, and internal amplifie rs for the selected channel. do es not enable the output. can only be done on a per channel basis. it is recommended to set this bit and allow a >200 s delay before enabling the output because this results in a re duced output enable glitch. see figure 29 and figure 47 for plots of this glitch. clr_en per channel clear enable bit. selects if this channel clears when the clear pin is activated. clr_en = 1, channel clears when the part is cleared. clr_en = 0, channel does not clear when the part is cleared (default). outen enables/disables the selected output channel. outen = 1, enables channel. outen = 0, disables channel (default). rset selects an internal or external current sense resistor for the selected dac channel. rset = 0, selects the external resistor (default). rset = 1, selects the internal resistor. dc_dc powers the dc-to-dc converter on the selected channel. dc_dc = 1, powers up the dc-to-dc converter. dc_dc = 0, powers down the dc-to-dc converter (default). this allows per channel dc-to-dc converter power-up/down. to power down the dc-to-dc converter, the outen and int_enable bits must also be set to 0. all dc-to-dc converters can also be powered up simultaneously using the dcdc_all bit in the main control register. ovrng enables 20% overrange on vo ltage output channel only. no curr ent output overrange available. ovrng = 1, enabled. ovrng = 0, disabled (default). r2, r1, r0 selects the output range to be enabled. r2 r1 r0 output range selected 0 0 0 0 v to 5 v voltage range (default). 0 0 1 0 v to 10 v voltage range. 0 1 0 5 v voltage range. 0 1 1 10 v voltage range. 1 0 0 4 ma to 20 ma current range. 1 0 1 0 ma to 20 ma current range. 1 1 0 0 ma to 24 ma current range.
ad5755 rev. 0 | page 36 of 48 software register the software register has three functions. it allows the user to perform a software reset to the part. it can be used to set the user toggle bit, d11, in the status register. it is also used as part of the watchdog feature when it is enabled. this feature is useful to ensure that communication has not been lost between the mcu and the ad5755 and that the datapath lines are working properly (that is, sdi, sclk, and sync ). when the watchdog feature is enabled, the user must write 0x195 to the software register within the timeout period. if this command is not received within the timeout period, the alert pin signals a fault condition. this is only required when the watchdog timer function is enabled. dc-to-dc control register the dc-to-dc control register allows the user control over the dc-to-dc switching frequency and phase, as well as the maximum allowable dc-to-dc output voltage. the dc-to-dc control register options are shown in table 24 and table 25 . table 22. programming the software register msb lsb d15 d14 d13 d12 d11 to d0 1 0 0 user program reset code/spi code table 23. software register functions bit description user program this bit is mapped to bit d11 of the status register. when this bit is set to 1, bit d11 of the status register is set to 1. likewise, when d12 is set to 0, bit d11 of the status register is also set to zero. this feature can be used to ensure that the spi pins are working correctl y by writing a known bit value to this register and reading back the corresponding bit from the status register. reset code/spi code option description reset code writing 0x555 to d[11:0] performs a reset of the ad5755. spi code if the watchdog timer feature is enabled, 0x195 must be written to the software register (d11 to d0) within the pr ogrammed timeout period. table 24. programming the dc-to-dc control register msb lsb d15 d14 d13 d12 to d7 d6 d5 to d4 d3 to d2 d1 to d0 0 1 1 x 1 dc-dc comp dc-dc phase dc-dc freq dc-dc maxv 1 x = dont care. table 25. dc-to-dc control register options bit description dc-dc comp selects between an internal and external compensation resistor for the dc-to-dc converter. see the dc-to-dc converter compensation capacitors and aicc supply requirementsslewing sections in the device features section for more information. 0 = selects the internal 150 k compensation resistor (default). 1 = bypasses the internal compensation resistor for the dc-to-dc converter. in this mode, an external dc-to-dc compensation resistor must be us ed; this is placed at the comp dcdc_x pin in series with the 10 nf dc-to-dc compensation capacitor to ground. typically, a ~50 k resistor is recommended. dc-dc phase user programmable dc-to-dc converter phase (between channels). 00 = all dc-to-dc converters clock on same edge (default). 01 = channel a and channel b clock on same edge, channel c and channel d clock on opposite edge. 10 = channel a and channel c clock on same edge, channel b and channel d clock on opposite edge. 11 = channel a, channel b, channel c, and channel d clock 90 out of phase from each other. dc-dc freq dc-to-dc switching frequency; these are divide d down from the internal 13 mhz oscillator (see figure 68 and figure 69 ). 00 = 250 10% khz. 01 = 410 10% khz (default). 10 = 650 10% khz. dc-dc maxv maximum allowed v boost_x voltage supplied by the dc-to-dc converter. 00 = 23 v + 1 v/?1.5 v (default). 01 = 24.5 v 1 v. 10 = 27 v 1 v. 11 = 29.5 v 1v.
ad5755 rev. 0 | page 37 of 48 slew rate control register th is register is used to program the slew rate control for the selected dac channel. this feature is available on both the current and voltage outputs. the slew rate control is enabled/ disabled and programmed on a per channel basis. see tabl e 26 and the device features section for more information. readback operation readback mode is invoked by setting the r/ w bit = 1 in the serial input register write. see for the bits associated with a readback operation. the dut_ad1 and dut_ad0 bits, in association with bits rd[4:0], select the register to be read. the remaining data bits in the write sequence are dont cares. during the next spi transfer (see ), the data appearing on the sdo output contains the data from the previously addressed register. this second spi transfer should either be a request to read yet another register on a third data transfer or 0x1ce000, which is the no operation command. table 27 figure 4 readback example to read back the gain register of device 1, channel a on the ad5755, implement the following sequence: 1. write 0xa80000 to the ad5755 input register. this configures the ad5755 device address 1 for read mode with the gain register of channel a selected. all the data bits, d15 to d0, are dont cares. 2. follow with another read command or a no operation command (0x1ce000). during this command, the data from the channel a gain register is clocked out on the sdo line. table 26. programming the slew rate control register d15 d14 d13 d12 d11 to d7 d6 to d3 d2 to d0 0 0 0 se x 1 sr_clock sr_step 1 x = dont care. table 27. input shift register contents for a read operation d23 d22 d21 d20 d19 d18 d17 d16 d15 to d0 r/ w dut_ad1 dut_ad0 rd4 rd3 rd2 rd1 rd0 x 1 1 x = dont care. table 28. read address decoding rd4 rd3 rd2 rd1 rd0 function 0 0 0 0 0 read dac a data register 0 0 0 0 1 read dac b data register 0 0 0 1 0 read dac c data register 0 0 0 1 1 read dac d data register 0 0 1 0 0 read dac a control register 0 0 1 0 1 read dac b control register 0 0 1 1 0 read dac c control register 0 0 1 1 1 read dac d control register 0 1 0 0 0 read dac a gain register 0 1 0 0 1 read dac b gain register 0 1 0 1 0 read dac c gain register 0 1 0 1 1 read dac d gain register 0 1 1 0 0 read dac a offset register 0 1 1 0 1 read dac b offset register 0 1 1 1 0 read dac c offset register 0 1 1 1 1 read dac d offset register 1 0 0 0 0 clear dac a code register 1 0 0 0 1 clear dac b code register 1 0 0 1 0 clear dac c code register 1 0 0 1 1 clear dac d code register 1 0 1 0 0 dac a slew rate control register 1 0 1 0 1 dac b slew rate control register 1 0 1 1 0 dac c slew rate control register 1 0 1 1 1 dac d slew rate control register 1 1 0 0 0 read status register 1 1 0 0 1 read main control register 1 1 0 1 0 read dc-to-dc control register
ad5755 rev. 0 | page 38 of 48 status register the status register is a read only register. this register contains any fault information as a well as a ramp active bit and a user toggle bit. when the statread bit in the main control register is set, the status register contents can be read back on the sdo pin during every write sequence. alternatively, if the statread bit is not set, the status register can be read using the normal readback operation. table 29. decoding the status register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dc- dcd dc- dcc dc- dcb dc- dca user toggle pec error ramp active over temp v out_d fault v out_c fault v out_b fault v out_a fault i out_d fault i out_c fault i out_b fault i out_a fault table 30. status register options bit description dc-dcd in current output mode, this bit is set on channel d if the dc-to-dc converter cannot maintain compliance (it may be reaching its v max voltage). in this case, the i out_d fault bit is also set. see the dc-to-dc converter vmax functionality section for more information on this bits operation under this condition. in voltage output mode, this bit is set if, on channel d, the dc-to-dc converter is unable to regulate to 15 v as expected. when this bit is set, it does not result in the fault pin going high. dc-dcc in current output mode, this bit is set on channel c if the dc-to-dc converter cannot maintain compliance (it may be reaching its v max voltage). in this case, the i out_c fault bit is also set. see the dc-to-dc converter vmax functionality section for more information on this bits operation under this condition. in voltage output mode, this bit is set if, on channel c, the dc-to-dc converter is unable to regulate to 15 v as expected. when this bit is set, it does not result in the fault pin going high. dc-dcb in current output mode, this bit is set on channel b if the dc-to-dc converter cannot maintain compliance (it may be reaching its v max voltage). in this case, the i out_b fault bit is also set. see the dc-to-dc converter vmax functionality for more information on this bits operation under this condition. in voltage output mode, this bit is set if, on channel b, the dc-to-dc converter is unable to regulate to 15 v as expected. when this bit is set, it does not result in the fault pin going high. dc-dca in current output mode, this bit is set on channel a if the dc-to-dc converter cannot maintain compliance (it may be reaching its v max voltage). in this case, the i out_a fault bit is also set. see the dc-to-dc converter vmax functionality for more information on this bits operation under this condition. in voltage output mode, this bit is set if, on channel a, the dc-to-dc converter is unable to regulate to 15 v as expected. when this bit is set, it does not result in the fault pin going high. user toggle user toggle bit. this bit is set or cleared via the software register. this can be used to verify data communicati ons if needed. pec error denotes a pec error on the last data-word received over the spi interface. ramp active this bit is set while any one of the output channels is slewing (slew rate control is enabled on at least one chann el). over temp this bit is set if the ad5755 core temperature exceeds approximately 150c. v out_d fault this bit is set if a fault is detected on the v out_d pin. v out_c fault this bit is set if a fault is detected on the v out_c pin. v out_b fault this bit is set if a fault is detected on the v out_b pin. v out_a fault this bit is set if a fault is detected on the v out_a pin. i out_d fault this bit is set if a fault is detected on the i out_d pin. i out_c fault this bit is set if a fault is detected on the i out_c pin. i out_b fault this bit is set if a fault is detected on the i out_b pin. i out_a fault this bit is set if a fault is detected on the i out_a pin.
ad5755 rev. 0 | page 39 of 48 d evice features output fault the ad5755 is equipped with a fault pin, an active low open- drain output allowing several ad5755 devices to be connected together to one pull-up resistor for global fault detection. the fault pin is forced active by any one of the following fault scenarios: ? the voltage at i out_x attempts to rise above the compliance range due to an open-loop circuit or insufficient power supply voltage. the internal circuitry that develops the fault output avoids using a comparator with windowed limits because this requires an actual output error before the fault output becomes active. instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 v of remaining drive capability. thus, the fault output activates slightly before the compliance limit is reached. ? a short is detected on a voltage output pin. the short- circuit current is limited to 16 ma or 8 ma, which is programmable by the user. if using the ad5755 in unipolar supply mode, a short-circuit fault may be generated if the output voltage is below 50 mv. ? an interface error is detected due to a pec failure. see the packet error checking section. ? if the core temperature of the ad5755 exceeds approximately 150c. the v out_x fault, i out_x fault, pec error, and over temp bits of the status register (see table 30 ) are used in conjunction with the fault output to inform the user which one of the fault conditions caused the fault output to be activated. voltage output short-circuit protection under normal operation, the voltage output sinks/sources up to 12 ma and maintains specified operation. the maximum output current or short-circuit current is programmable by the user and can be set to 16 ma or 8 ma. if a short circuit is detected, the fault goes low, and the relevant short cct bit in the status register is set. digital offset and gain control each dac channel has a gain (m) and offset (c) register, which allow trimming out of the gain and offset errors of the entire signal chain. data from the dac data register is operated on by a digital multiplier and adder controlled by the contents of the m and c registers. the calibrated dac data is then stored in the dac input register. dac register dac input register m register c register 07304-075 figure 76. digital offset and gain control although figure 76 indicates a multiplier and adder for each channel, there is only one multiplier and one adder in the device, and they are shared among all four channels. this has implications for the update speed when several channels are updated at once (see table 3 ). each time data is written to the m or c register, the output is not automatically updated. instead, the next write to the dac channel uses these m and c values to perform a new calibration and automatically updates the channel. the output data from the calibration is routed to the dac input register. this is then loaded to the dac as described in the theory of operation section. both the gain register and the offset register have 16 bits of resolution. the correct method to calibrate the gain/offset is to first calibrate out the gain and then calibrate the offset. the value (in decimal) that is written to the dac input register can be calculated by 15 16 2 2 )1( ?+ + = c m d code rdacregiste (1) where: d is the code loaded to the input register of the dac channel. m is the code in the gain register (default code = 2 16 C 1). c is the code in the offset register (default code = 2 15 ). status readback during a write the ad5755 has the ability to read back the status register contents during every write sequence. this feature is enabled via the statread bit in the main control register. this allows the user to continuously monitor the status register and act quickly in the case of a fault. when status readback during a write is enabled, the contents of the 16-bit status register (see table 30 ) are output on the sdo pin, as shown in figure 5 . the ad5755 powers up with this feature disabled. when this is enabled, the normal readback feature is not available, except for the status register. to read back any other register, clear the statread bit first before following the readback sequence. statread can be set high again after the register read.
ad5755 rev. 0 | page 40 of 48 asynchronous clear clear is an active high, edge-sensitive input that allows the output to be cleared to a preprogrammed 16-bit code. this code is user programmable via a per channel 16-bit clear code register. for a channel to clear, that channel must be enabled to be cleared via the clr_en bit (see table 21 ) in the channels dac control register. if the channel is not enabled to be cleared, then the output remains in its current state independent of the clear pin level. when the clear signal is returned low, the relevant outputs remain cleared until a new value is programmed. packet error checking to verify that data has been received correctly in noisy environ- ments, the ad5755 offers the option of packet error checking based on an 8-bit (crc-8) cyclic redundancy check. the device controlling the ad5755 should generate an 8-bit frame check sequence using the polynomial c ( x ) = x 8 + x 2 + x 1 + 1 this is added to the end of the data-word, and 32 bits are sent to the ad5755 before taking sync high. if the ad5755 sees a 32-bit frame, it performs the error check when sync goes high. if the check is valid, the data is written to the selected register. if the error check fails, the fault pin goes low and the pec error bit in the status register is set. after reading the status register, fault returns high (assuming there are no other faults), and the pec error bit is cleared automatically. sdin sync sclk update on sync high msb d23 lsb d0 24-bit data 24-bit data transfer?no error checking sdin fault sync sclk update after sync high only if error check passed fault pin goes high if error check fails msb d31 lsb d8 d7 d0 24-bit data 8-bit crc 32-bit data transfer with error checking 07304-180 figure 77. pec timing the pec can be used for both transmit and receive of data packets. if status readback during a write is enabled, the pec values returned during the status readback during a write operation should be ignored. if status readback during a write is disabled, the user can still use the normal readback operation to monitor status register activity with pec. watchdog timer when enabled, an on-chip watchdog timer generates an alert signal if 0x195 has not been written to the software register within the programmed timeout period. this feature is useful to ensure that communication has not been lost between the mcu and the ad5755 and that these datapath lines are working properly (that is, sdi, sclk, and sync ). if 0x195 is not received by the software register within the timeout period, the alert pin signals a fault condition. the alert signal is active high and can be connected directly to the clear pin to enable a clear in the event that communication from the mcu is lost. the watchdog timer is enabled, and the timeout period (5 ms, 10 ms, 100 ms, or 200 ms) is set in the main control register (see table 18 and table 19 ). output alert the ad5755 is equipped with an alert pin. this is an active high cmos output. the ad5755 also has an internal watchdog timer. when enabled, it monitors spi communications. if 0x195 is not received by the software register within the timeout period, the alert pin goes active. internal reference the ad5755 contains an integrated 5 v voltage reference with initial accuracy of 5 mv maximum and a temperature drift coefficient of 10 ppm maximum. the reference voltage is buffered and externally available for use elsewhere within the system. external current setting resistor referring to figure 72 , r set is an internal sense resistor as part of the voltage-to-current conversion circuitry. the stability of the output current value over temperature is dependent on the stability of the value of r set . as a method of improving the stability of the output current over temperature, an external 15 k low drift resistor can be connected to the r set_x pin of the ad5755 to be used instead of the internal resistor, r1. the external resistor is selected via the dac control register (see table 20 ). table 1 outlines the performance specifications of the ad5755 with both the internal r set resistor and an external, 15 k r set resistor. using an external r set resistor allows for improved performance over the internal r set resistor option. the external r set resistor specification assumes an ideal resistor; the actual performance depends on the absolute value and temperature coefficient of the resistor used. this directly affects the gain error of the output, and thus the total unadjusted error. to arrive at the gain/tue error of the output with a particular external r set resistor, add the percentage absolute error of the r set resistor directly to the gain/tue error of the ad5755 with the external r set resistor, shown in tabl e 1 (expressed in % fsr).
ad5755 rev. 0 | page 41 of 48 digital slew rate control the slew rate control feature of the ad5755 allows the user to control the rate at which the output value changes. this feature is available on both the current and voltage outputs. with the slew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached load. to reduce the slew rate, this can be achieved by enabling the slew rate control feature. with the feature enabled via the sren bit of the slew rate control register (see table 26 ), the output, instead of slewing directly between two values, steps digitally at a rate defined by two parameters accessible via the slew rate control register, as shown in table 26 . the parameters are sr_clock and sr_step. sr_clock defines the rate at which the digital slew is updated, for example, if the selected update rate is 8 khz, the output updates every 125 s. in conjunc- tion with this, sr_step defines by how much the output value changes at each update. together, both parameters define the rate of change of the output value. table 31 and table 32 outline the range of values for both the sr_clock and sr_step parameters. table 31. slew rate update clock options sr_clock update clock frequency (hz) 1 0000 64 k 0001 32 k 0010 16 k 0011 8 k 0100 4 k 0101 2 k 0110 1 k 0111 500 1000 250 1001 125 1010 64 1011 32 1100 16 1101 8 1110 4 1111 0.5 1 these clock frequencies are divided down from the 13 mhz internal oscillator. see table 1 , figure 68 , and figure 69 . table 32. slew rate step size options sr_step step size (lsbs) 000 1 001 2 010 4 011 16 100 32 101 64 110 128 111 256 the following equation describes the slew rate as a function of the step size, the update clock frequency, and the lsb size: sizelsb frequency clock update sizestep change output timeslew = where: slew time is expressed in seconds. output change is expressed in amps for i out_x or volts for v out_x . when the slew rate control feature is enabled, all output changes occur at the programmed slew rate (see the dc-to-dc converter settling time section for additional information). for example, if the clear pin is asserted, the output slews to the clear value at the programmed slew rate (assuming that the clear channel is enabled to be cleared). if a number of channels are enabled for slew, care must be taken when asserting the clear pin. if one of the channels is slewing when clear is asserted, other channels may change directly to their clear values not under slew rate control. the update clock frequency for any given value is the same for all output ranges. the step size, however, varies across output ranges for a given value of step size because the lsb size is different for each output range. power dissipation control the ad5755 contains integrated dynamic power control using a dc-to-dc boost converter circuit, allowing reductions in power consumption from standard designs when using the part in current output mode. in standard current input module designs, the load resistor values can range from typically 50 to 750 . output module systems must source enough voltage to meet the compliance voltage requirement across the full range of load resistor values. for example, in a 4 ma to 20 ma loop when driving 20 ma, a compliance voltage of >15 v is required. when driving 20 ma into a 50 load, only 1 v compliance is required. the ad5755 circuitry senses the output voltage and regulates this voltage to meet compliance requirements plus a small headroom voltage. the ad5755 is capable of driving up to 24 ma through a 1 k load. dc-to-dc converters the ad5755 contains four independent dc-to-dc converters. these are used to provide dynamic control of the v boost supply voltage for each channel (see figure 72 ). figure 78 shows the discreet components needed for the dc-to-dc circuitry, and the following sections describe component selection and operation of this circuitry. av cc l dcdc d dcdc c dcdc 4.7f c filter 0.1f r filter c in sw x v boost_x ? 10f 10? 10h 07304-077 figure 78. dc-to-dc circuit
ad5755 rev. 0 | page 42 of 48 table 33. recommended dc-to-dc components symbol component value manufacturer l dcdc xal4040-103 10 h coilcraft? c dcdc grm32er71h475ka88l 4.7 f murata d dcdc pmeg3010bea 0.38 v f nxp it is recommended to place a 10 , 100 nf low-pass rc filter after c dcdc . this consumes a small amount of power but reduces the amount of ripple on the v boost_x supply. dc-to-dc converter operation the on-board dc-to-dc converters use a constant frequency, peak current mode control scheme to step up an av cc input of 4.5 v to 5.5 v to drive the ad5755 output channel. these are designed to operate in discontinuous conduction mode (dcm) with a duty cycle of <90% typical. discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. the dc-to-dc converters are nonsynchronous; that is, they require an external schottky diode. dc-to-dc converter output voltage when a channel current output is enabled, the converter regulates the v boost_x supply to 7.4 v (5%) or (i out r load + headroom), whichever is greater (see figure 52 for a plot of headroom supplied vs. output current). in voltage output mode with the output disabled, the converter regulates the v boost_x supply to +15 v (5%). in current output mode with the output disabled, the converter regulates the v boost_x supply to 7.4 v (5%). within a channel, the v out_x and i out_x stages share a common v boost_x supply so that the outputs of the i out_x and v out_x stages can be tied together. dc-to-dc converter settling time when in current output mode, the settling time for a step greater than ~1v (i out r load ) is dominated by the settling time of the dc-to-dc converter. the exception to this is when the required voltage at the i out_x pin plus the compliance voltage is below 7.4 v (5%). a typical plot of the output settling time can be found in figure 48 . this plot is for a 1 k load. the settling time for smaller loads is faster. the settling time for current steps less than 24 ma is also faster. dc-to-dc converter v max functionality the maximum v boost_x voltage is set in the dc-to-dc control register (23 v, 24.5 v, 27 v, or 29.5 v; see table 25 ). on reaching this maximum voltage, the dc-to-dc converter is disabled, and the v boost_x voltage is allowed to decay by ~0.4 v. after the v boost_x voltage has decayed by ~0.4 v, the dc-to-dc converter is reenabled, and the voltage ramps up again to v max , if still required. this operation is shown in figure 79 . 28.6 28.7 28.8 28.9 29.0 29.1 29.2 29.3 29.4 29.5 29.6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v boost_x voltage (mv) time (ms) v max 0ma to 24ma range, 24ma output output unloaded dc-dc maxv = 29.5v dc_dc bit dc-dcx bit = 0 dc-dcx bit = 1 f sw = 410khz t a = 25c 07304-183 figure 79. operation on reaching v max as can be seen in figure 79 , the dc-dcx bit in the status register asserts when the ad5755 is ramping to the v max value, but deasserts when the voltage is decaying to v max ? ~0.4 v. dc-to-dc converter on-board switch the ad5755 contains a 0.425 internal switch. the switch current is monitored on a pulse by pulse basis and is limited to 0.8 a peak current. dc-to-dc converter switching frequency and phase the ad5755 dc-to-dc converter switching frequency can be selected from the dc-to-dc control register. the phasing of the channels can also be adjusted so that the dc-to-dc converter can clock on different edges (see table 25 ). for typical applications, a 410 khz frequency is recommended. at light loads (low output current and small load resistor), the dc-to-dc converter enters a pulse-skipping mode to minimize switching power dissipation. dc-to-dc converter inductor selection for typical 4 ma to 20 ma applications, a 10 h inductor (such as the xal4040-103 from coilcraft), combined with a switch- ing frequency of 410 khz, allows up to 24 ma to be driven into a load resistance of up to 1 k with an av cc supply of 4.5 v to 5.5 v. it is important to ensure that the inductor is able to handle the peak current without saturating, especially at the maximum ambient temperature. if the inductor enters into saturation mode, it results in a decrease in efficiency. the inductance value also drops during saturation and may result in the dc-to-dc converter circuit not being able to supply the required output power. dc-to-dc converter external schottky selection the ad5755 requires an external schottky for correct opera- tion. ensure that the schottky is rated to handle the maximum reverse breakdown expected in operation and that the rectifier maximum junction temperature is not exceeded. the diode average current is approximately equal to the i load current. diodes with larger forward voltage drops result in a decrease in efficiency.
ad5755 rev. 0 | page 43 of 48 dc-to-dc converter compensation capacitors as the dc-to-dc converter operates in dcm, the uncompensated transfer function is essentially a single-pole transfer function. the pole frequency of the transfer function is determined by the dc-to-dc converters output capacitance, input and output voltage, and output load. the ad5755 uses an external capacitor in conjunction with an internal 150 k resistor to compensate the regulator loop. alternatively, an external compensation resistor can be used in series with the compensation capacitor, by setting the dc-dc comp bit in the dc-to-dc control register. in this case, a ~50 k resistor is recommended. a description of the advantages of this can be found in the aicc supply requirementsslewing section in the device features section. for typical applications, a 10 nf dc-to-dc compensation capacitor is recommended. dc-to-dc converter input and output capacitor selection the output capacitor affects ripple voltage of the dc-to-dc converter and indirectly limits the maximum slew rate at which the channel output current can rise. the ripple voltage is caused by a combination of the capacitance and equivalent series resistance (esr) of the capacitor. for the ad5755, a ceramic capacitor of 4.7 f is recommended for typical applications. larger capacitors or paralleled capacitors improve the ripple at the expense of reduced slew rate. larger capacitors also impact the av cc supplies current requirements while slewing (see the aicc supply requirementsslewing section). this capaci- tance at the output of the dc-to-dc converter should be >3 f under all operating conditions. the input capacitor provides much of the dynamic current required for the dc-to-dc converter and should be a low esr component. for the ad5755, a low esr tantalum or ceramic capacitor of 10 f is recommended for typical applications. ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature. x5r or x7r dielectrics are preferred because these capacitors remain stable over wider operating voltage and temperature ranges. care must be taken if selecting a tantalum capacitor to ensure a low esr value. ai cc supply requirementsstatic the dc-to-dc converter is designed to supply a v boost voltage of v boost = i out r load + headroom (2) see figure 52 for a plot of headroom supplied vs. output voltage. this means that, for a fixed load and output voltage, the output current of the dc-to-dc converter can be calculated by the following formula: cc v boost out cc cc av vi av efficiency outpower ai boost = = (3) where: i out is the output current from i out_x in amps. v boost is the efficiency at v boost_x as a fraction (see figure 54 and figure 55 ). ai cc supply requirementsslewing the ai cc current requirement while slewing is greater than in static operation because the output power increases to charge the output capacitance of the dc-to-dc converter. this transient current can be quite large (see figure 80 ), although the methods outlined in the reducing aicc current requirements section can reduce the requirements on the av cc supply. if not enough ai cc current can be provided, the av cc voltage drops. due to this av cc drop, the ai cc current required to slew increases further. this means that the voltage at av cc drops further (see equation 3) and the v boost voltage, and thus the output voltage, may never reach its intended value. because this av cc voltage is common to all channels, this may also affect other channels. 0 5 10 15 20 25 30 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.5 1.0 1.5 2.0 2.5 i out_x current (ma)/v boost_x voltage (v) ai cc current (a) time (ms) ai cc i out v boost 0ma to 24ma range 1k ? load f sw = 410khz inductor = 10h (xal4040-103) t a = 25c 07304-184 figure 80. ai cc current vs. time for 24 ma slew with internal compensation resistor reducing ai cc current requirements there are two main methods that can be used to reduce the ai cc current requirements. one method is to add an external compensation resistor, and the other is to use slew rate control. both of these methods can be used in conjunction. a compensation resistor can be placed at the comp dcdc_x pin in series with the 10 nf compensation capacitor. a 51 k exter- nal compensation resistor is recommended. this compensation increases the slew time of the current output but eases the ai cc transient current requirements. figure 81 shows a plot of ai cc current for a 24 ma step through a 1 k load when using a 51 k compensation resistor. this method eases the current requirements through smaller loads even further, as shown in figure 82 .
ad5755 rev. 0 | page 44 of 48 0 4 12 8 16 24 20 28 32 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ai cc current (a) 0ma to 24ma range 1k ? load f sw = 410khz inductor = 10h (xal4040-103) t a = 25c 0 0.5 1.0 1.5 2.0 2.5 i out_x current (ma)/v boost_x voltage (v) time (ms) ai cc i out v boost 07304-185 figure 81. ai cc current vs. time for 24 ma through 1 k slew with external 51 k compensation resistor 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ai cc current (a) 0ma to 24ma range 500 ? load f sw = 410khz inductor = 10h (xal4040-103) t a = 25c 0 4 12 8 16 24 20 28 32 0 0.5 1.0 1.5 2.0 2.5 i out_x current (ma)/v boost_x voltage (v) time (ms) ai cc i out v boost 07304-186 figure 82. ai cc current vs. time for 24 ma through 500 slew with external 51 k compensation resistor using slew rate control can greatly reduce the av cc supplies current requirements, as shown in figure 83. when using slew rate control, attention should be paid to the fact that the output cannot slew faster than the dc-to-dc converter. the dc-to-dc converter slews slowest at higher currents through large (for example, 1 k) loads. this slew rate is also dependent on the dc-to-dc converter configuration. two examples of the dc-to-dc converter output slew are shown in figure 81 and figure 82 (v boost corresponds to the dc-to-dc converters output voltage). 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ai cc current (a) 0ma to 24ma range 1k? load f sw = 410khz inductor = 10h (xal4040-103) t a = 25c 0 4 12 8 16 24 20 28 32 01 2345 6 i out_x current (ma)/v boost_x voltage (v) time (ms) ai cc i out v boost 07304-187 figure 83. ai cc current vs. time for 24 ma slew with slew rate control
ad5755 rev. 0 | page 45 of 48 applications information voltage and current output ranges on the same terminal when using a channel of the ad5755, the current and voltage output pins can be connected to two separate terminals or tied together and connected to a single terminal. there is no conflict with tying the two output pins together because only the voltage output or the current output can be enabled at any one time. when the current output is enabled, the voltage output is in tristate mode, and when the voltage output is enabled, the current output is in tristate mode. for this operation, the poc pin must be tied low and the poc bit in the main control register set to 0, or, if the poc pin is tied high, the poc bit in the main control register must be set to 1 before the current output is enabled. as shown in the absolute maximum ratings section, the output tolerances are the same for both the voltage and current output pins. the +v sense_x and ?v sense_x connections are buffered so that current leakage into these pins is negligible when in current output mode. current output mode with internal r set when using the internal r set resistor in current output mode, the output is significantly affected by how many other channels using the internal r set are enabled and by the dc crosstalk from these channels. the internal r set specifications in table 1 are for all channels enabled with the internal r set selected and outputting the same code. for every channel enabled with the internal r set , the offset error decreases. for example, with one current output enabled using the internal r set , the offset error is 0.075% fsr. this value decreases proportionally as more current channels are enabled; the offset error is 0.056% fsr on each of two channels, 0.029% on each of three channels, and 0.01% on each of four channels. similarly, the dc crosstalk when using the internal r set is propor- tional to the number of current output channels enabled with the internal r set . for example, with the measured channel at 0x8000 and one channel going from zero to full scale, the dc crosstalk is ?0.011% fsr. with two channels going from zero to full scale, it is ?0.019% fsr, and with all three other channels going from zero to full scale, it is ?0.025% fsr. for the full-scale error measurement in table 1 , all channels are at 0xffff. this means that, as any channel goes to zero scale, the full-scale error increases due to the dc crosstalk. for example, with the measured channel at 0xffff and three channels at zero scale, the full-scale error is 0.025%. similarly, if only one channel is enabled in current output mode with the internal r set , the full-scale error is 0.025% fsr + 0.075% fsr = 0.1% fsr. precision voltage reference selection to achieve the optimum performance from the ad5755 over its full operating temperature range, a precision voltage reference must be used. thought should be given to the selection of a precision voltage reference. the voltage applied to the reference inputs is used to provide a buffered reference for the dac cores. therefore, any error in the voltage reference is reflected in the outputs of the device. there are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long term drift, and output voltage noise. initial accuracy error on the output voltage of an external refer- ence can lead to a full-scale error in the dac. therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. choosing a reference with an output trim adjustment, such as the adr425, allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. the trim adjust- ment can be used at any temperature to trim out any error. long-term drift is a measure of how much the reference output voltage drifts over time. a reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. the temperature coefficient of a references output voltage affects inl, dnl, and tue. a reference with a tight temperature coefficient specification should be chosen to reduce the depend- ence of the dac output voltage to ambient temperature. in high accuracy applications, which have a relatively low noise budget, reference output voltage noise must be considered. choosing a reference with as low an output noise voltage as practical for the system resolution required is important. precision voltage references such as the adr435 (xfet design) produce low output noise in the 0.1 hz to 10 hz region. however, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. table 34. recommended precision references part no. initial accuracy (mv maximum) long-term drift (ppm typical) temperature drift (ppm/c maximum) 0.1 hz to 10 hz noise (v p-p typical) adr445 2 50 3 2.25 adr02 3 50 3 10 adr435 2 40 3 8 adr395 5 50 9 8 ad586 2.5 15 10 4
ad5755 rev. 0 | page 46 of 48 driving inductive loads when driving inductive or poorly defined loads, a capacitor may be required between i out_x and agnd to ensure stability. a 0.01 f capacitor between i out_x and agnd ensures stability of a load of 50 mh. the capacitive component of the load may cause slower settling, although this may be masked by the set- tling time of the ad5755. there is no maximum capacitance limit for the current output of the ad5755. transient voltage protection the ad5755 contains esd protection diodes that prevent dam- age from normal handling. the industrial control environment can, however, subject i/o circuits to much higher transients. to protect the ad5755 from excessively high voltage transients, external power diodes and a surge current limiting resistor are required, as shown in figure 84 . the two protection diodes and resistor must have appropriate power ratings. further protection can be provided with transient voltage suppressors or transorbs; these are available as both unidirectional suppressors (protect against positive high voltage transients) and bidirectional suppres- sors (protect against both positive and negative high voltage transients) and are available in a wide range of standoff and breakdown voltage ratings. it is recommended that all field connected nodes be protected. r load r p ad5755 v boost_x v boost_x i out_x gnd 07304-079 figure 84. output transient voltage protection microprocessor interfacing microprocessor interfacing to the ad5755 is via a serial bus that uses a protocol compatible with microcontrollers and dsp processors. the communications channel is a 3-wire minimum interface consisting of a clock signal, a data signal, and a latch signal. the ad5755 requires a 24-bit data-word with data valid on the falling edge of sclk. the dac output update is initiated on either the rising edge of ldac or, if ldac is held low, on the rising edge of sync . the contents of the registers can be read using the readback function. ad5755-to-adsp-bf527 interface the ad5755 can be connected directly to the sport interface of the adsp-bf527, an analog devices, inc., blackfin? dsp. figure 85 shows how the sport interface can be connected to control the ad5755. 07304-080 ad5755 sync sclk sdin ldac sport_tfs sport_tsck sport_dto gpio0 adsp-bf527 figure 85. ad5755-to-adsp-bf527 sport interface layout guidelines layoutgrounding in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5755 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5755 is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the gndsw x and ground connection for the av cc supply are referred to as pgnd. pgnd should be confined to certain areas of the board, and the pgnd-to-agnd connection should be made at one point only. layoutsupply decoupling the ad5755 should have ample supply bypassing of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esl), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. layouttraces t he power supply lines of the ad5755 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to prevent radiating noise to other parts of the board and should never be run near the reference inputs. a ground line routed between the sdin and sclk lines helps reduce crosstalk between them (not required on a multilayer board that has a separate ground plane, but separating the lines helps). it is essential to minimize noise on the refin line because it couples through to the dac output. a void crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough on the board. a microstrip technique is by far the best but not always possible with a double-sided board. in this technique, the component
ad5755 rev. 0 | page 47 of 48 galvanically isolated interface side of the board is dedicated to ground plane, whereas signal traces are placed on the solder side. in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. isocouplers provide voltage isolation in excess of 2.5 kv. the serial loading structure of the ad5755 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 86 shows a 4-channel isolated interface to the ad5755 using an adum1400 . for more information, visit www.analog.com . l ayoutdc-to-dc converters t o achieve high efficiency, good regulation, and stability, a well- designed printed circuit board layout is required. f ollow these guidelines when designing printed circuit boards (see figure 78 ): ? keep the low esr input capacitor, c in , close to av cc and pgnd. ? keep the high current path from c in through the inductor, l dcdc , to sw x and pgnd as short as possible. v ia serial clock out to sclk v oa encode decode v ib serial data out to sdin v ob encode decode v ic sync out v oc encode decode v id control out v od encode decode microcontroller adum1400* *additional pins omitted for clarity. to sync to ldac 07304-081 ? keep the high current path from c in through l dcdc , the rectifier, d dcdc , and the output capacitor, c dcdc , as short as possible. ? keep high current traces as short and as wide as possible. the path from c in through the inductor, l dcdc , to sw x and pgnd should be able to handle a minimum of 1 a. ? place the compensation components as close as possible to comp dcdc_x . figure 86. isolated interface ? avoid routing high impedance traces near any node connected to sw x or near the inductor to prevent radiated noise injection.
ad5755 rev. 0 | page 48 of 48 outline dimensions compliant to jedec standards mo-220-vmmd-4 080108-c 0.25 min top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max exposed pad (bottom view) seating plane pin 1 indicator 7.25 7.10 sq 6.95 pin 1 indicator 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 87. 64-lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp-64-3) dimensions shown in millimeters ordering guide model 1 resolution (bits) temperature range package description package option ad5755acpz-reel7 16 ?40c to +105c 64-lead lfcsp_vq cp-64-3 AD5755BCPZ-REEL7 16 ?40c to +105c 64-lead lfcsp_vq cp-64-3 1 z = rohs compliant part. ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07304-0-5/11(0)

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